FR2404301A1 - SILICON INTEGRATED CIRCUITS ON PLANAR SAPPHIRE AND PRODUCTION METHOD OF SUCH INTEGRATED CIRCUITS - Google Patents

SILICON INTEGRATED CIRCUITS ON PLANAR SAPPHIRE AND PRODUCTION METHOD OF SUCH INTEGRATED CIRCUITS

Info

Publication number
FR2404301A1
FR2404301A1 FR7827087A FR7827087A FR2404301A1 FR 2404301 A1 FR2404301 A1 FR 2404301A1 FR 7827087 A FR7827087 A FR 7827087A FR 7827087 A FR7827087 A FR 7827087A FR 2404301 A1 FR2404301 A1 FR 2404301A1
Authority
FR
France
Prior art keywords
integrated circuits
gates
sapphire
silicon
production method
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
FR7827087A
Other languages
French (fr)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
RCA Corp
Original Assignee
RCA Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by RCA Corp filed Critical RCA Corp
Publication of FR2404301A1 publication Critical patent/FR2404301A1/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H01L21/2652—Through-implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H01L21/86—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body the insulating body being sapphire, e.g. silicon on sapphire structure, i.e. SOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76281—Lateral isolation by selective oxidation of silicon

Abstract

L'invention concerne des circuits intégrés CIS sur un substrat isolant comme du saphir ou du spinelle, employant des portes conductrices en silicium polycristallin. Selon l'invention, afin de produire des dispositifs ayant de faibles courants de fuite, on utilise une température d'oxydation inférieure à 1000 degrés C pour produire l'oxyde de champ 38 et l'oxyde de porte 36. De plus, on utilise des techniques d'implantation d'ions pour doper les sources et les drains 18, 20, 28, 30 des transistors 12, 14. L'utilisation de portes 24, 34 en silicium polycristallin dopé du type N + permet d'utiliser, comme getter, du dioxyde de silicium dopé au phosphore et donne également des portes ayant une conductivité supérieure aux portes dopées du type P+. L'invention s'applique notamment aux circuits intégrés silicium sur saphir.Disclosed are CIS integrated circuits on an insulating substrate such as sapphire or spinel, employing conductive gates of polysilicon. According to the invention, in order to produce devices having low leakage currents, an oxidation temperature below 1000 degrees C is used to produce the field oxide 38 and the gate oxide 36. In addition, use is made of ion implantation techniques for doping the sources and the drains 18, 20, 28, 30 of the transistors 12, 14. The use of gates 24, 34 of N + type doped polysilicon makes it possible to use, as getter, silicon dioxide doped with phosphorus and also gives gates having higher conductivity than P + doped gates. The invention applies in particular to silicon-on-sapphire integrated circuits.

FR7827087A 1977-09-22 1978-09-21 SILICON INTEGRATED CIRCUITS ON PLANAR SAPPHIRE AND PRODUCTION METHOD OF SUCH INTEGRATED CIRCUITS Withdrawn FR2404301A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US83559077A 1977-09-22 1977-09-22

Publications (1)

Publication Number Publication Date
FR2404301A1 true FR2404301A1 (en) 1979-04-20

Family

ID=25269903

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7827087A Withdrawn FR2404301A1 (en) 1977-09-22 1978-09-21 SILICON INTEGRATED CIRCUITS ON PLANAR SAPPHIRE AND PRODUCTION METHOD OF SUCH INTEGRATED CIRCUITS

Country Status (5)

Country Link
JP (1) JPS5456774A (en)
DE (1) DE2839933A1 (en)
FR (1) FR2404301A1 (en)
GB (1) GB2005073A (en)
IT (1) IT7826422A0 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0568475A1 (en) * 1992-04-30 1993-11-03 International Business Machines Corporation Method of forming thin silicon mesas having uniform thickness

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55148467A (en) * 1979-05-10 1980-11-19 Nec Corp Sos cmos semiconductor device and its manufacture
US4523368A (en) * 1980-03-03 1985-06-18 Raytheon Company Semiconductor devices and manufacturing methods
JPS56126936A (en) * 1980-03-12 1981-10-05 Toshiba Corp Semiconductor device and production thereof
GB2081018B (en) * 1980-07-31 1985-06-26 Suwa Seikosha Kk Active matrix assembly for display device
JPS5754371A (en) * 1980-09-19 1982-03-31 Toshiba Corp Manufacture of semiconductor device
JPS58176967A (en) * 1982-04-12 1983-10-17 Toshiba Corp Preparation of semiconductor device
US5316960A (en) * 1989-07-11 1994-05-31 Ricoh Company, Ltd. C-MOS thin film transistor device manufacturing method
US5930638A (en) * 1993-07-12 1999-07-27 Peregrine Semiconductor Corp. Method of making a low parasitic resistor on ultrathin silicon on insulator
US5973363A (en) * 1993-07-12 1999-10-26 Peregrine Semiconductor Corp. CMOS circuitry with shortened P-channel length on ultrathin silicon on insulator
US5864162A (en) * 1993-07-12 1999-01-26 Peregrine Seimconductor Corporation Apparatus and method of making a self-aligned integrated resistor load on ultrathin silicon on sapphire
US5863823A (en) * 1993-07-12 1999-01-26 Peregrine Semiconductor Corporation Self-aligned edge control in silicon on insulator

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CH495632A (en) * 1968-08-13 1970-08-31 Siemens Ag Field effect transistor

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CH495632A (en) * 1968-08-13 1970-08-31 Siemens Ag Field effect transistor

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
EXBK/77 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0568475A1 (en) * 1992-04-30 1993-11-03 International Business Machines Corporation Method of forming thin silicon mesas having uniform thickness

Also Published As

Publication number Publication date
JPS5456774A (en) 1979-05-08
IT7826422A0 (en) 1978-08-02
GB2005073A (en) 1979-04-11
DE2839933A1 (en) 1979-04-05

Similar Documents

Publication Publication Date Title
US4011105A (en) Field inversion control for n-channel device integrated circuits
US4272880A (en) MOS/SOS Process
US4382827A (en) Silicon nitride S/D ion implant mask in CMOS device fabrication
GB1465244A (en) Deep depletion insulated gate field effect transistors
GB1261723A (en) Improvements in and relating to semiconductor devices
US4038107A (en) Method for making transistor structures
US4402761A (en) Method of making self-aligned gate MOS device having small channel lengths
FR2404301A1 (en) SILICON INTEGRATED CIRCUITS ON PLANAR SAPPHIRE AND PRODUCTION METHOD OF SUCH INTEGRATED CIRCUITS
KR20010101506A (en) Lateral thin-film soi device having a lateral drift region and method of making such a device
EP0032700A2 (en) JFET device
US4532697A (en) Silicon gigabit metal-oxide-semiconductor device processing
US4596068A (en) Process for minimizing boron depletion in N-channel FET at the silicon-silicon oxide interface
US3450961A (en) Semiconductor devices with a region having portions of differing depth and concentration
US6001677A (en) Method for fabricating CMOS transistors by implanting into polysilicon
US4783423A (en) Fabrication of a semiconductor device containing deep emitter and another transistor with shallow doped region
JPS59151464A (en) Metal insulator semiconductor transistor and manufacture thereof
JPH04276662A (en) Manufacture of semiconductor device
GB2038088A (en) Semiconductor structures
JP2515524B2 (en) Method for manufacturing insulating gate field effect transistor
JPH01268061A (en) Semiconductor device
JPH0350771A (en) Semiconductor device
JPH0878684A (en) Semiconductor device and its manufacture
JPH08321603A (en) Field-effect semiconductor device and manufacturing method thereof
JPS6112390B2 (en)
JPS58157169A (en) Semiconductor device

Legal Events

Date Code Title Description
ST Notification of lapse