DE2839933A1 - INTEGRATED CIRCUIT WITH INSULATING SUBSTRATE - Google Patents

Description

Dn.-lng. Reimar King Dipi.-lng. Klaus Bergen

Cecilienallee ~ 7G A Düsseldorf 3Q phone 452DQB patent attorneys

September 12, 1978 32,472 B

RCA Corporation, 30 Rockefeller Plaza,

New York, N.Y. 10020 (V.St.A.)

"Integrated circuit with insulating substrate"

The invention relates to an integrated circuit with an insulating substrate and at least one in an isolated (individual), semiconducting island on a main surface of the substrate formed, each with a source, a channel zone and a drain and one lying on the channel zone Channel insulator and a CIS transistor thereon, made of conductive semiconductor material, having a gate, and also a surrounding each island and the island surface formed on the substrate main surface as a substantially coplanar surface continuing insulating material area (field oxide). The invention also relates to a method of manufacturing an integrated circuit by forming a semiconductor layer on a major surface an insulating substrate, removing parts of the semiconductor layer down to the main surface of the substrate, Production of islands surrounding the semiconductor layer and surfaces essentially coplanar to the surface thereof having insulating material areas (field oxides) at the location of the previously removed parts of the semiconductor layer, and forming CIS transistors on the islands each having a drain and a source region of the one and a channel zone of the other conductivity type, a channel oxide located at least on the channel zone and one on the latter lying conductive semiconductor gate.

609814/0742

-t-

2839833

Built Pur aforementioned integrated Haibleiterschaltkreise, ■ for example, in Silizium.-AAF SAPM r-Techn Ik (SOS technology) complementary conductor Isalatar-semiconductor devices (CIS devices), the simultaneous ¥ orliegen high working speed * low power and flexible structural design typical. Difficulties in the manufacture of high-performance SOS circuit bags result from the high leakage current, the thin metal coating on oxide levels and the low breakdown voltage of the gate oxide. The difficulties relating to the thin metal coating of the oxide stages and the low breakdown voltage at the gate oxide are due to the topography characterized by isolated (individual) islands, as is customary in SOS integrated circuits.

In order to overcome these disadvantages, it has been proposed to manufacture SOS components using a planar technique. A such a planar process in which gate electrodes are made of metal are used is described in the magazine "Electronics" from May 26, 1977, pages 99-105. After this Known methods can be manufactured integrated circuits, in which the problems relating to the metal stratification and the low breakdown voltage no longer occur. The problem with the an acceptable level exceeding leakage currents remain.

The invention is based on the object of creating an integrated circuit of the type mentioned at the beginning, in which also the leakage currents are reduced to a tolerable level. For the integrated circuit itself, there is the one according to the invention The solution to the problem is that a layer of undoped silicon dioxide on the surface of each The transistor is located and the insulating material area surrounds the transistors (laterally, coherently) and that on

80Ö8U / O742

the layer of undoped silicon dioxide a layer of silicon dioxide doped with phosphorus lies.

The invention provides a high performance SOS circuit has been created with relatively low leakage current and relatively high breakdown voltage of the gate oxide, which because of the planar structure, there are no longer any problems with regard to the coating of oxide stages. The planar structure results from the fact that the insulating material areas (field oxides) are essentially the same As high as the semiconducting islands and the latter coherently encompassing the periphery.

The object on which the invention is based is also achieved by the above-mentioned method for producing an integrated Circuit released when applied to the surface of the transistors and the areas of insulating material or field oxides an undoped silicon dioxide layer and deposited on this a phosphorus-doped layer of silicon dioxide will.

The importance of the last-mentioned phosphor glass layer is, among other things, its getter effect against impurities, e.g. sodium, which can impair the function of the circuit. It is particularly advantageous in this connection, if during the deposition of the layer doped with phosphorus at least about 4 wt .-% Phosphorus can be introduced into the layer.

Based on the schematic representation of an embodiment of the integrated circuit and the G * an of the Manufacturing process further details of the invention are explained.

ÖÖ98U / OH2

-U-

Show it:

1 shows a cross section through an integrated circuit according to the invention? and

FIGS. 2 ″ to 9 show cross-sections through the semiconductor component in various stages of manufacture.

In Fig. 1, part of a cross section of an integrated circuit 10 according to the invention is shown. In addition Circuit 10 includes an N-channel transistor 12 and a P-channel transistor 14. Both transistors 12 and 14 are CIS transistors preferably formed on a substrate 16 from sapphire.

The N-channel transistor 12 contains an N ⁺ -conducting source 18 and an N ⁺ -conducting drain 20. The last-mentioned two zones are separated by a P ~ -conducting channel zone 22. On the channel zone 22 there is a ^ -conducting, polycrystalline silicon gate 24, which is separated from the channel zone 22 by a thin gate oxide 26.

The P-channel transistor 14 has a P ⁺ -type source 28 and a P ⁺ -type drain 30. These two zones are separated from one another by an N ~ -channel zone 32. A thin gate oxide 36 lies on the channel zone 32 and an N ⁺ -doped, polycrystalline silicon gate 34 lies on it. The latter has essentially the same thickness as the transistors 12 and 14. The integrated circuit 10 thus has an essentially flat or planar surface.

eOddU / 0742

- Sr -

An undoped silicon dioxide layer lies on the field oxide 38 43 and a phosphorus-doped silicon dioxide layer 39 · One of these layers extends through each of these layers Row of contact holes 37. The phosphorus-doped silicon dioxide layer 39 acts as a getter (barrier). This keeps contaminants such as sodium away, which would otherwise prevent the integrated circuit from working 10 could affect. Metal conductors 41 extend through the contact holes and contact them Sources, drains and gates of transistors 12 and 14.

According to FIG. 2, for producing the integrated circuit 10 of Fig. 1 with a substrate 16 made of an insulating Material such as single crystal aluminum oxide (Al 0)

2 3 - called sapphire - should be started, whichever is preferred is cut parallel to the (1TO2) crystal plane. Spinel can also be used instead of sapphire.

During the manufacture of the integrated circuit 10, an undoped epitaxial layer 42 of monocrystalline silicon with an orientation parallel to the (100) crystal axis up to a thickness of approximately 600 μm can first be grown on the main surface 40 of the substrate 16. The epitaxial layer 42 is then carefully cleaned in a cleaning solution known as “Standard Clean - # * 1” ( hereinafter “SC jf 1”). The cleaning solution SC $ t 1 is made from one part hydrogen peroxide (H ₂ O ₂ ), one part ammonium hydroxide (NH ^ OH) and three parts distilled water (H ₂ O). The epitaxial layer 42 is then carefully treated in a second cleaning solution known as “Standard Clean f 2” (hereinafter “SC t 2”). This second cleaning solution consists of one part hydrogen peroxide (H ₂ O ₂ ) and one part hydrogen chloride

2833933

(HCl) and three parts of water (BUQ) .. The cleaning in the cleaning solutions SC ^ 1 and SC ψ ~ 2 is completed by boiling the substrate, including the layers on it, in each of the solutions.

The substrate with one or more applied. Layers are referred to below as "slices". After cleaning, the wafer is placed in an oven containing an oxidizing agent and a small amount of HCl to grow a clean silicon dioxide (SiOp) layer 44 to a thickness of about 20 nm on the surface of the silicon layer 42. The silicon dioxide layer 44 is preferably grown at a furnace temperature of about 900 ⁰ C.

A thin silicon nitride (SiJ ^) layer 46 is deposited on the surface of the silicon dioxide layer 44 by the reaction of silane (SiH.) With nitrogen (Np) and ammonia (NH3). The nitride layer can be deposited in a disk reactor ("pancake style" reactor), for example in the model 800 manufactured by Applied Materials, Inc., Santa Clara, California, USA. The nitride layer 46 can be grown in a period of 3 to 5 minutes and at a temperature of 800 ^° C. to a thickness of approximately 50 nm. Nitride layers with a thickness of only a few tenths of a nanometer can also be used. The components to be produced, however, are most flat when silicon nitride layers 46 with a thickness of approximately 200 nm are used.

A mask is then placed on the surface of the silicon nitride layer 46 as a mask for etching the silicon nitride layer 46 provided silicon dioxide layer 45 is deposited. The production of the silicon dioxide layer 45 can

909014/0742

-T-

be carried out by reaction of iron silane with oxygen in a heated to about 300 ⁰ C oven.

, Then on the silicon dioxide layer 45 is a Photoresist layer applied and so limited and developed, that the locations where the transistors 12 and 14 are formed are covered by masks 48 and 50 ". The parts of the not covered by the masks 43 and 50 " Surface of the disc or the silicon dioxide layer

45 are now etched with buffered hydrofluoric acid (HF) at a temperature of about 27 ° C. until the silicon nitride layer 46 is exposed. The masks 48 and 50 are then removed, and the parts of the silicon dioxide layer 45 remaining under the masks serve as a mask for further etching. Here, the silicon nitride layer is etched in heated to about 180 ⁰ C phosphoric 46th During this treatment, the parts of the silicon nitride layer not lying under the remaining areas of the silicon dioxide layer 45 become

46 removed.

Next, the remaining parts of the silicon nitride layer 46 are used as a mask for etching the silicon dioxide layer 44 in buffered HF at about 27 ^° C. and then the remaining parts of the silicon dioxide layer 44 are used as a mask for etching the silicon layer 42 in one of n- Propanol and potassium hydroxide (KOH) existing solution is used. The parts of the silicon layer 42 that are not below the remaining parts of the silicon nitride layer 46 are etched until their remaining layer thickness is a little more than 45-6 of the original layer thickness. The disc is then cleaned in the cleaning solutions SC ^ 1 and SC / "2 as described above.

9Ö98U / 0U2

The state of the wafer after the silicon layer 42 has been etched is shown in FIG. In this state, the disc is placed in a furnace containing an oxidizing atmosphere with, among other things, steam and a small amount of HCl. For the minimization of the leakage currents of the transistors to be produced, which is desired according to the invention, it has proven to be critical or important when oxidizing the exposed parts of the silicon layer 42 and thus when forming the isolated silicon islands 52 and 54 provided for receiving the transistors 12 and 14 (Fig. 4) surrounding field oxides 38 ι
to adjust.

Field oxides 38 have a furnace temperature below about 1000 ° C

The oxidizing of the leading to the formation of the field oxides 38 Silicon layer 42 is continued until all exposed parts of silicon layer 42 are oxidized. The field oxide 38 will have a slightly greater thickness than the silicon islands 52 and 54 because it is completely oxidized Silicon is about 2.22 times as thick as unoxidized silicon. So after parts of the field oxides 38 during removal of silicon dioxide layers 44 and 45 are removed, the surfaces of silicon islands 52 and 54 and the field oxides 38 lie essentially in one plane, i.e. have a planar structure.

It has been found that the above mentioned oxidizing at a furnace temperature of about 1000 ⁰ C for two hours, at a furnace temperature of about 950 ⁰ C for about four hours and brought for eight hours at a furnace temperature of about 900 ⁰ C for about. Following the oxidation, all parts of the silicon dioxide layer 45 remaining on the surface of the silicon nitride layer 46 are removed with the aid of buffered HF at about 27 ° C.

909814/07 * 2

- ar-

Next, the silicon nitride layer 46 is put in place Removed about 180 ° C heated phosphoric acid. After finally the remaining parts of the silicon dioxide layer 44 have been removed with the help of buffered HF at about 27 ° C, the disc according to Fig.

According to FIG. 5, the surface of the disc is now following process step covered with a photoresist layer 56 with a thickness of about 600 nm. The photoresist layer 56 is limited and developed so that that provided for making the N-channel transistor 12 is provided Island 52 is exposed. Then the surface of the disc is subjected to an ion implantation of acceptors, e.g. boron (indicated by the arrows in Fig. 5) to dope the exposed island 52 and it To make P ~ conductive. The ion implantation is preferably carried out with boron ions with an energy of about 70 KeV, in order to obtain an acceptor dose of about 7 × 10 atoms / cm in the exposed island 52.

According to FIG. 6, the photoresist layer 56 is then removed and the wafer is subjected to ion implantation by donors (shown by the arrows) in order to dope the previously unexposed island 54 and make it N ~ -conductive. The ion implantation is carried out in such a way that the island 52, which has already been doped with P ~, is not redoped into the N line. In this second ion implantation, phosphorus ions are therefore preferably implanted with an energy of approximately 170 KeV until a donor concentration of approximately 1 10 8 atoms / cm ^{2 is} established. Following the ion implantation, the disc is ^{tempered or heated in helium at about 105O 0} C for a period of 15 minutes in order to transfer the implanted defects or impurities more evenly into the

eOöÖU / 0742

- Jö-

Diffuse silicon. This is followed by cleaning with the cleaning agents SC 5 ^ 1 and SC ff * 2.

Channel oxides 26 and 36 are now grown on islands 52 and 54 to a thickness of about 120 m. This step is done in a steam and a small amount of HCl containing furnace whose temperature must be below 1000 ⁰ C. For example, the channel can be oxides at a temperature of 950 ⁰ C for a period of 30 minutes or at a temperature of 900 ⁰ C in about 60 minutes and 36 ^ 26
nis is shown in FIG.

900 ⁰ C can be grown in about 60 minutes. The result

Next, a polycrystalline silicon layer 58 is deposited on the surface of the wafer to a thickness of about 0.6 micrometers. The polycrystalline silicon layer 58 is preferably deposited by pyrolytic deposition of silane (SiH,) at a temperature between approximately 650 and 700 ^° C.

In a preferred embodiment of the invention, the polycrystalline silicon layer is ⁺ doped 58 with the aid of a phosphorus-iPOCl ^ J-method in a heated to about 1025 ⁰ C oven N -conductive that a sheet resistance of about gives 15 0hm / square. The POCl ₇₅ process consists of three stages. _{Initially, N 2} and O ₂ flow into the furnace over a period of about 5 minutes. Next, the POCl, source is turned on for about three minutes. This is followed by tempering in nitrogen (N ₂ ) for a period of about three minutes.

Although it is possible, instead of the N ⁺ -type doped layer 58, one to form P ⁺ -type gates

909014/0742

-Vi-

To use leading, P ⁺ -leHfcencL doped polycrystalline silicon layer, Έ -conductively doped gates are preferred ^{for various reasons. First, a P +} -le ± tendes polycrystalline material has an area resistance "of about 50 ohms / square while N -doped polycrystalline Silicon has a sheet resistance of 15 ohms / square. Furthermore, phosphorus acts as a getter against impurities such as sodium, which can cause shifts in the threshold energy or voltage of the N-channel transistor to significant advantages with regard to the stability of the component produced.

All silicon dioxide layers grown in the POCl ^ process are now removed with the help of hydrofluoric acid. Then the disc is again in the detergent SC / "1 and SC ^ 2 cleaned.

In a next method step, a silicon dioxide layer 60 is deposited on the polycrystalline silicon layer 58, for example by reaction of silane and oxygen at about 300 ^° C., up to a layer thickness of about 50 nm. A photoresist layer 62 is then formed on the silicon dioxide layer 60. This is limited and developed, and the silicon dioxide layer 60 is etched in buffered hydrofluoric acid at 27 ° C. in such a way that masks (not shown) are produced on the areas of the polycrystalline silicon layer 58 provided for the gates 24 and 34. The photoresist layer 62 is then removed again and the polycrystalline silicon layer 58 is etched in potassium hydroxide (KOH). The corresponding etching stops at the channel oxides 26 and 36 and at the field oxides 38. After the subsequent removal of the silicon dioxide layer 60 in a buffered

Ä0Ö8U / 0U2

HF at about 27 ° C., the gates 24 and 34 remain on the disk according to FIG. 8.

Next, another photoresist layer 64 with a thickness of about 600 nm is produced on the wafer, limited and designed so that the one for the N-channel transistor 12 provided area is exposed. In order to prevent the photoresist layer 64 in the subsequent If a strong implantation dose breaks, the layer 64 becomes one for a period of 5 minutes at 150.degree Subsequent heat treatment. The disk then becomes an ion implantation represented by the arrows from donors, e.g. phosphorus, of about

15/2 170 KeV up to a dose of 2 χ 10 ^J atoms / cm in order to form the N ⁺ -conducting source 18 and the N ⁺ -conducting drain 20 of the transistor 12 according to FIG. 8. The channel zone 22 of the transistor 12 retains the P ~ line because it is masked by the gate 24.

The photoresist layer 64 is then removed, for example with the aid of a plasma peeling machine (plasma stripper). A new photoresist layer 66 is now applied to the wafer, for example by baking, is delimited and developed in such a way that the area provided for the P-channel transistor 14 according to FIG. 9 is exposed. The disc is then subjected to ion implantation by acceptors indicated by the arrows. For example, boron ions of about 70 KeV up to a dose of about 2 × 10 ^ atoms / cm can be implanted in such a way that the P ⁺ -conducting source 28 and the P ⁺ -conducting drain 30 of the P-channel transistor 14 develop. The photoresist layer 66 is then removed in the same way as the photoresist layer 64. The channel zone 32 of the transistor 14 retains

909814/0742

its N- line because it is masked by gate 64, and the gate retains its N ^{+ line} because its dopant concentration is much greater than that implanted in source 28 and drain 30.

After the transistors 12 and 14 have been formed, a thin protective oxide or an undoped silicon dioxide layer 43 with a thickness of approximately 100 μm is deposited on the surface of the wafer. This undoped silicon dioxide layer 43 prevents the P ⁺ -conducting sources and drains of the P-channel transistor from being redoped during the subsequent heat treatment. A phosphorus-doped silicon dioxide layer 39 with a thickness of approximately 600 nm is then applied to the surface of the undoped silicon dioxide layer. The deposition of this oxide layer can be made by pyrolytic decomposition of silane at a temperature of about 300 ⁰ C. The phosphorus concentration in the doped silicon dioxide layer 39 should preferably be between approximately 4 and 8% by weight.

In the preferred embodiment of the invention, the disc is then cleaned in the aforementioned cleaning solutions SC Λ and SC ψ 2 and then placed in a POCl ^ oven heated to about 1075 ° C. in order to make the silicon dioxide flow. The three-stage POCl, process explained above is repeated in order to produce rounded edges of the silicon dioxide layer 39 which forms a glass layer and is doped with phosphorus. This process step, in which the phosphor glass is made to flow, is not necessary for the production of stable transistors with low leakage current, but it should result in an improved yield.

Ö0Ö6U / OU2

After the oxide layers 39 and 43 have been deposited, contact holes 37 can be formed in them. That can for example with the help of a photoresist layer and a mask and subsequent etching in buffered HF at a temperature of about 27 ° C. Next, a metal layer, e.g. an aluminum layer, are formed on the surface of the oxide layers. The metal layer can then be used to produce conductor tracks 41 to complete the integrated circuit 14.

Finally, an oxide layer (not shown) can be applied to the entire integrated circuit 10 will. Connection fields or holes can be produced in this oxide layer in a known manner.

A complementarily symmetrical integrated circuit has been described above. The invention but also refers to the manufacture of integrated circuits that either only have a P-channel or have only one N-channel.

SQ98U / QH2

Claims (3)

RCA Corporation, 30 Rockefeller Plaza, New York , NY 10020 (V.St.A.) Claims; ÜX Integrated circuit with an insulating substrate and at least one in an isolated (single) semiconducting island on a substrate major surface formed, a source, a channel zone and a drain as well as a channel insulator lying on the channel zone and a gate made of conductive semiconductor material thereon (CIS transistor), and also a surrounding each island and the island surface formed on the substrate main surface as a substantially coplanar surface continuing insulating material area, characterized that a layer (43) of undoped silicon dioxide lies on the surface of each transistor (12, 14) and the insulating material region (38) surrounds the transistors (12, 14), and that on the layer (43) of undoped silicon dioxide a layer (39) of silicon dioxide doped with phosphorus lies. 2. A method of manufacturing an integrated circuit by forming a semiconductor layer on a major surface an insulating substrate, removing parts of the semiconductor layer down to the main surface of the substrate Production of islands surrounding the semiconductor layer and essentially on its surface having coplanar surfaces §09814 / 0742 ORIGINAL INSPECTED '*' 283993? Areas of insulating material at the location of the previously removed portions of the semiconductor layer, and forming CIS transistors on the islands, each with a drain and a source zone of the one and a channel zone of the other conductivity type, a channel oxide lying at least on the channel zone and one the latter lying conductive semiconductor gate, characterized in that on the surface of the transistors (12, 14) and the insulating material regions (38) an undoped silicon dioxide layer (43) and on this a phosphorus-doped layer (39) made of silicon dioxide is deposited. 3. The method according to claim 2, characterized in that upon precipitation the layer (39) doped with phosphorus is introduced into the layer at least about 4% by weight of phosphorus will. 9 fu 9098U / 0742