JPH08321603A - Field-effect semiconductor device and manufacturing method thereof - Google Patents

Abstract

PURPOSE: To enable the threshold value voltage of a field effect semiconductor device to be stabilized in relation to the method of manufacturing the field effect semiconductor device. CONSTITUTION: Within the title field effect semiconductor device 10, the highest impurity concentration part 28 in the channel region opposite to a gate electrode 16 in a body region 30B is to be located in a position distant from the part where the body region 30B comes into contact with a source region 26. In such a constitution, since the highest impurity concentration part 28 is located in a position distant from the part where the channel region 30C opposite to the gate electrode 16 in the body region 30B comes into contact with the source region 26, even if the extension of the source region 26 is fluctuated, the highest impurity concentration part 28 is not affected at all. Accordingly, the part in the highest impurity concentration is located in an intermediate portion of the flow path of the electrons migrating in the channel region 30C, thereby stabilizing the threshold value voltage depending upon the highest impurity concentration.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect semiconductor device and a method of manufacturing the same, and more particularly to a technique for stabilizing the threshold voltage of the field effect semiconductor device.

[0002]

2. Description of the Related Art As an example of a conventional field effect semiconductor device, there is a vertical field effect semiconductor device as disclosed in Japanese Patent Laid-Open No. 56-73472, and a schematic view of this cross section is shown in FIG. Shown in. 18, a field effect semiconductor device 100 includes an n ⁺ type drain region 112, an n type drift region 110, a p type body region 120 and an n type drift region 110.
The source region 116 of ⁺ type is mainly configured.

A drain electrode 114 is provided in contact with the lower surface of the drain region 112, and a drift region 110 is formed on the upper surface thereof. A body region 120 is formed inside the drift region 110, and a source region 116 is formed inside the body region 120. On the other hand, the surface of the drift region 110, the surface of the body region 120, and the surface of the source region 116 are covered with an insulating film 108, and the gate electrode 106 is provided in contact with the surface side of the insulating film 108. Further, the gate electrode 106 is covered with an insulating film 104, and the source electrode 102 which is in contact with the source region 116 through the opening portion of the insulating film 104 is provided.

Impurities are introduced into the body region 120 by ion implantation and heat treatment in order to secure a predetermined threshold voltage. First, in ion implantation, ions are accelerated with low acceleration energy (40 KeV), and boron as an impurity (chemical symbol: chemical symbol: from a direction substantially perpendicular to the surface of the insulating film 108 on which the gate electrode 106 is formed).
B) is driven into the body region 120. Heat treatment (for example, 1100 ° C., 30 minutes) is performed to recover and activate the lattice defects generated by the ion implantation and diffuse the implanted impurities. Thus, the body region 12
The concentration of the impurities introduced into 0 has a curve (Gaussian distribution) as shown in FIG. That is, in FIG. 19, the horizontal axis represents the distance in the depth direction (downward in FIG. 18) from the boundary between the body region 120 and the insulating film 108, and the vertical axis represents the impurity concentration. Here, the highest impurity concentration D100 is located at a depth of a distance L100 from the surface.
In FIG. 8, a portion 118 is shown.

When operating the field effect semiconductor device 100 having the above structure, the source electrode 102 is grounded and the drain electrode 114 and the gate electrode 10 are grounded.
A positive voltage is applied to 6 and. Here, the gate electrode 106
When a voltage higher than the threshold voltage is applied to the insulating film 108,
Body region 1 facing the gate electrode 106 across the
An inversion layer (hereinafter referred to as “channel region”) is induced near the surface of 20. This channel region is the insulating film 1
08 is more likely to be induced as it approaches the boundary between the body region 120 and 08, and is less likely to be induced as the distance from the boundary is increased. Therefore, from the source region 116 to the drift region 11
Many electrons flowing to 0 flow along the surface of the body region 120 near the insulating film 108 as shown by the arrow E in FIG. 18, and reach the drain electrode 114 via the drain region 112. Hereinafter, the direction of current flowing in the channel region in parallel with the gate electrode is referred to as "channel current direction".

[0006]

In the width direction of the body region 120 in the conventional field effect semiconductor device 100, the concentration of impurities introduced into the body region 120 in the section C1-C2 shown in FIG. As the curve 20 indicates, the distance decreases from the source region 116 toward the drift region 110. This means that the degree of diffusion performed when forming the source region 116 (hereinafter,
It is called the “degree of spread”. ) Will affect the maximum impurity concentration. For example, as shown in FIG. 21, the boundary between the source region 116 and the body region 120 is
When the width changes from the portion L8b to the portion L12b centering on the portion L10b, the maximum impurity concentration also changes from the concentration D10c to the concentration D8c to the width D12c. Therefore, the maximum impurity concentration changes depending on the extent of the spread of the source region 116, and the threshold voltage also changes.

Therefore, in the conventional field effect semiconductor device, the threshold voltage cannot be stabilized. Such a change in the threshold voltage occurs not only on different wafers but also on the same wafer. The present invention has been made in view of such a point, and its problem is to provide a portion showing the maximum impurity concentration in the channel region at a position away from the boundary between the source region and the body region,
This is to prevent the maximum impurity concentration depending on the extent of the spread of the source region from being affected and thus stabilize the threshold voltage.

[0008]

According to a first aspect of the present invention, there is provided a first conductivity type source region and a drain region interposed between the first conductivity type source region and the drain region. A field-effect semiconductor device having a second conductivity type body region of conductivity type and a gate electrode facing the body region with an insulating layer in between, and a channel facing the gate electrode in the body region. The highest impurity concentration region in the region is located away from the region where the body region is in contact with the source region.

[0009]

According to the first aspect of the invention, in the channel region of the body region facing the gate electrode, the maximum impurity concentration region is located at a position distant from the region where the source region is in contact with the body region. Will exist. Therefore, even if the degree of spread of the source region varies, the maximum impurity concentration is not affected, and the threshold voltage can be stabilized.

[0010]

According to a second aspect of the present invention, there is provided a field effect semiconductor device manufacturing method, wherein a gate electrode is provided on a surface of a first conductivity type semiconductor substrate with an insulating layer interposed therebetween. A gate electrode forming step, a source region forming step of forming impurities of a shallow region of the semiconductor substrate to form the first conductive type source area in the gate electrode forming step, and a gate in the gate electrode forming step An impurity is introduced into a deep portion of the semiconductor substrate from an oblique direction with respect to the surface of the semiconductor substrate on which the electrodes are formed to activate the semiconductor substrate, and a second conductivity type of a conductivity type opposite to the first conductivity type is introduced. A body region forming step of forming a body region.

The source region forming process and the body region forming process can be performed in any order. Further, “introducing an impurity into a deep portion of a semiconductor substrate” means introducing an impurity into a portion that is deeper by a predetermined distance from the unevenness on the surface of the semiconductor substrate. Therefore, a large amount of impurities introduced into the deep portion exist in the portion along the uneven shape substantially similar to the uneven shape on the surface of the semiconductor substrate.

[0012]

According to the second aspect of the invention, in the body region forming step, the impurities are introduced into a deep portion of the semiconductor substrate from an oblique direction. By this introduction, a large amount of impurities are present at positions displaced in the horizontal direction and along the uneven shape substantially similar to the uneven shape on the surface of the semiconductor substrate. Therefore, in the channel region of the body region facing the gate electrode, a large amount of impurities are present at a portion horizontally displaced from the vertical wall of the gate electrode, and this is the highest impurity concentration portion. Therefore, the maximum impurity concentration is not affected even if the degree of spread of the source region is changed, so that the threshold voltage can be stabilized.

[0013]

An embodiment of the present invention will be described below with reference to the drawings. Regarding semiconductor process technology, a thermal oxidation method for forming an oxide film, a CV for forming a thin film by a chemical reaction
D (Chemical Vapor Deposition) method, photolithography method of transferring a fine pattern on a mask onto a wafer to form a resist pattern, RIE (Reactive Ion Etching) method of removing a thin film formed on a substrate, and a desired method An ion implantation method for implanting impurities into a semiconductor region,
The thermal diffusion method of introducing impurities into the substrate and the thin film, the PVD (Physical Vapor Deposition) method of physically forming a thin film, and the sputtering method of forming an alloy thin film are all related to each method. Since this is a known technique, detailed description thereof will be omitted. Further, in this embodiment, for simplification of description, a field effect semiconductor device in which the first conductivity type is n-type and the second conductivity type is p-type will be described.

A double-diffused metal oxide (DMOS), which is one of the field effect semiconductor devices 10.
Semiconductor) -FET (Field Effect Transistor)
) Is shown in FIG. This field effect semiconductor device 10 is similar to the field effect semiconductor device 100 described above.
an n ⁺ type drain region 22, an n type drift region 20,
p type body region 30B and n ⁺ type source region 26
It is mainly composed of. In comparison with the field effect semiconductor device 100, the specific configuration is such that the drain region 22 is the drain region 112, the drain electrode 24 is the drain electrode 114, and the drift region 20 is the drift region 1.
10, the body region 30B is the body region 120, the source region 26 is the source region 116, the insulating film 18 is the insulating film 108, the gate electrode 16 is the gate electrode 106, the insulating film 14 is the insulating film 104, and the source electrode. Reference numerals 12 correspond to the source electrodes 102, respectively.

Here, the highest impurity concentration portion 28 in the body region 30B has a horizontal portion along the surface of the insulating film 18 and a vertical portion along the surface (vertical wall) of the gate electrode 16. The vertical portion of the highest impurity concentration portion 28 reaches the boundary portion between the insulating film 18 and the body region 30B. By the way, when the source electrode 12 is grounded, a positive voltage is applied to the drain electrode 24, and a voltage equal to or higher than a threshold voltage is applied to the gate electrode 16, the body facing the gate electrode 16 with the insulating film 18 interposed therebetween is provided. A channel region 30C is induced near the surface of the region 30B.

From this fact, the highest impurity concentration region 28 always exists in the channel region 30C. That is, the section A1 in the channel current direction shown in FIG.
As for the impurity concentration of −A2, as shown in FIG. 2, the impurity concentration at the portion L10 that is the boundary between the source region 26 and the body region 30B and at the portion L30 that is the boundary between the body region 30B and the drain region 22 is: Highest impurity concentration part 28
The impurity concentration is less than D20. In this example, the impurity concentration in the n ⁺ type source region 26 is the concentration D30, and the impurity concentration in the n ⁺ type drain region 22 is the concentration D10.

The field effect semiconductor device 1 having the above structure
At 0, the maximum impurity concentration in the channel region 30C is not affected even by the extent of spread when forming the source region 26. That is, as shown in FIG.
The boundary between the source region 26 and the body region 30B is the portion L
Even if the width varies from the portion L8a to the portion L12a centering on 10a, the maximum impurity concentration is the maximum impurity concentration portion 28.
Is the impurity concentration D20. Therefore, even if the degree of spread of the source region 26 changes, the highest impurity concentration region 28 is not affected. Therefore, the channel region 30
A portion having the highest impurity concentration always exists in the middle of the flow path of electrons flowing through C, and the threshold voltage depending on the highest impurity concentration can be stabilized.

Next, a method of manufacturing the field effect semiconductor device 10 will be described with reference to FIGS. [First Insulating Film Forming Step] First, as shown in FIG. 4, a low concentration n type drift region 20 is epitaxially grown on a high concentration n ⁺ type semiconductor substrate (drain region 22).
Further, an insulating film (oxide film) 18 is formed on the surface of the drift region 20 by a thermal oxidation method. [Gate Electrode Forming Step] Next, as shown in FIG. 5, a gate electrode {polycrystalline silicon film containing a large amount of phosphorus (chemical symbol: P)} 16 is deposited on the surface of the insulating film 18 by a CVD method.

[Source Region Forming Step] Then, as shown in FIG. 6, by using the photolithography method and the RIE method,
The gate electrode 16 is formed in a predetermined pattern. After the pattern formation, if the gate electrode 16 is sufficiently thick, the resist film 40 used in the pattern formation may be removed. After that, arsenic (chemical symbol: As) as an impurity is implanted from the direction substantially perpendicular to the surface of the insulating film 18 by an ion implantation method, and the n ⁺ type source region 2 is formed.
6 is formed.

[Body Region Forming Step] Further, as shown in FIG. 7, boron (chemical symbol: B) as an impurity is obliquely implanted into the surface of the insulating film 18 by an oblique ion implantation method, and p A mold body region 30B is formed. For example, ions are accelerated with high acceleration energy and boron is implanted into the surface of the insulating film 18 from the direction of 45 degrees. Here, when performing the oblique ion implantation method, as shown in FIG.
Impurity is injected only diagonally. At this time, the gate electrode 1
It is necessary to make the angle and the acceleration energy such that the portion where the impurities are obliquely injected from the surface (vertical wall) of 6 by the projection range L reaches the boundary between the insulating film 18 and the body region 30B. By doing so, the highest impurity concentration region 28 can be secured in the channel region 30C induced near the surface of the body region 30B facing the gate electrode 16 with the insulating film 18 interposed therebetween.

After removing the resist film 40, the source region 2 is subjected to a low temperature heat treatment (for example, 900 ° C., 30 minutes) or a short time high temperature heat treatment (for example, 1100 ° C., 30 seconds).
6 and the impurity implanted into the body region 30B are hardly diffused, and the lattice defects generated by the ion implantation are recovered and activated (annealed).

[Second Insulating Film Forming Step] Then, as shown in FIG. 9, an insulating film (oxide film) 14 containing a large amount of phosphorus is deposited on the surface of the gate electrode 16 by the CVD method. Then, as shown in FIG. 10, photolithography and RI are performed.
The insulating film 14 is formed into a predetermined pattern by using the E method.

[Source Electrode Forming Step] Then, as shown in FIG. 11, the source region 26 is etched by RIE using the insulating film 14 as a mask. Then, a metal such as aluminum (chemical symbol: Al) is deposited by a sputtering method to form the source electrode 12, and the field effect semiconductor device 10 shown in FIG. 1 is completed. In the manufacturing process, the source region forming process and the body region forming process that are performed after the gate electrode forming process can be performed in any order.

In this manufacturing method, the angle is set such that the portion into which the impurity is obliquely injected from the surface (vertical wall) of the gate electrode 16 by the projection range L reaches the boundary between the insulating film 18 and the body region 30B. , Highest impurity concentration part 2
8 can be secured in the channel region 30C. Moreover, the highest impurity concentration portion 28 is formed in the body region 30.
B will be present at a position away from the portion in contact with the source region 26. Therefore, even if the degree of spread of the source region 26 changes, the highest impurity concentration portion 28 is not affected, and the threshold voltage depending on the concentration of the highest impurity concentration portion 28 can be stabilized.

Here, in the present invention, in addition to the effect of stabilizing the threshold voltage described above, the effect of stabilizing the value of the punch-through voltage is additionally provided. The reason for this will be described below. First, in manufacturing the conventional field-effect semiconductor device 100 shown in FIG. 18, when the drift region 110 is epitaxially grown, a shift in the concentration ratio between the silane (Si H ₄ ) gas and the phosphine (PH ₃ ) gas, The impurity concentration also changes according to the temperature change of those gases. That is, as shown in FIG. 13, the concentration of the drift region 110 changes in the range from the concentration D10b to the concentration D8b to the concentration D12b. At this time, the boundary between the body region 120 and the drift region 110 is the portion L30.
The width varies from the portion L28b to the portion L32b centering on b. Therefore, the value of the punch-through voltage depending on the widthwise distance in the body region 120 also changes.

Even in the case of the field effect semiconductor device 10 of the present invention shown in FIG. 1, the impurity concentration also changes depending on the gas concentration ratio and the temperature change. However, since the impurity concentration curve in the body region 30B is a convex curve having the highest impurity concentration in the region L20, the slope of the impurity concentration curve is steep at the boundary between the body region 30B and the drift region 20. Therefore, when viewed from the same change in impurity concentration in the drift region 110 as in the conventional field effect semiconductor device 100, as shown in FIG. 12, the boundary between the body region 30B and the drift region 20 is centered on the site L30a and is located on the site L28a.
To the part L32a, the fluctuation range is small. Therefore, the variation of the distance in the width direction in the body region 30B becomes small, so that the value of the punch-through voltage depending on the distance in the width direction can be stabilized.

A field effect semiconductor device 50 having a second structure to which the present invention is applied will be described with reference to FIG. FIG. 14 shows an example of a lateral double-diffused MOS.
(LDMOS; Lateral Double-diffused MOS) -FET
The cross-sectional structure of is shown. The same elements as those of the field-effect semiconductor device 10 (double diffusion MOS-FET) shown in FIG. 1 are designated by the same reference numerals, and the description of those elements will be omitted. Here, the field effect semiconductor device 50 shown in FIG. 14 is different from the field effect semiconductor device 10 shown in FIG. 1 in that the drain region 22 is opposed to the body region 30B in the channel current direction with the drift region 20 interposed therebetween. It is the point that is formed. That is, the drain region 22 is formed inside the body region 30 </ b> B in contact with the source region 26, and the surface of the drain region 22 is covered with the insulating film 18. The drain electrode 24 is in contact with the insulating film 18 through the opening. In the field effect semiconductor device 50 having such a configuration, the change in the impurity concentration in the widthwise section A3-A4 shown in FIG. 14 is as shown in FIG.

A field effect semiconductor device 60 having a third structure to which the present invention is applied will be described with reference to FIG. FIG. 16 shows an example of the vertical U-groove MOS (VU
MOS; Vertical U-grooved MOS) -FET sectional structure. The field effect semiconductor device 10 shown in FIG.
The same elements as those of the (double diffused MOS-FET) are designated by the same reference numerals, and the description of the elements will be omitted.
Here, the field effect semiconductor device 60 shown in FIG.
The difference from the field effect semiconductor device 10 shown in FIG. 2 is that the gate electrode 1 extends over the body region 30B and the drift region 20.
6 is formed in a columnar shape with the insulating film 18 interposed therebetween. In the field effect semiconductor device 60 having such a configuration, the section A5-A in the channel current direction shown in FIG.
The change in the impurity concentration of No. 6 is as shown in FIG.

Here, as is clear from the change in impurity concentration shown in FIGS. 15 and 17, the impurities are induced near the surface of the p-type body region 30B facing the gate electrode 16 with the insulating film 18 in between. The highest impurity concentration portion 28 surely exists in the channel region 30C, and the source region 26
Unaffected by varying degrees of spread. Therefore, even with the configuration of the field effect semiconductor devices 50 and 60, the threshold voltage can be stabilized similarly to the field effect semiconductor device 10. In addition, the value of the punch-through voltage can be stabilized additionally.

Although one embodiment of the field effect semiconductor device and the manufacturing method thereof has been described above, the structure, shape, size, material, number and arrangement of the other parts in this field effect semiconductor device and the manufacturing method thereof are described. , Operating conditions,
The manufacturing procedure and the like are not limited to those in this embodiment. For example, although the present invention is applied to the double diffusion MOS-FET, the horizontal double diffusion MOS-FET, and the vertical U-groove MOS-FET, the invention is not limited to these field effect semiconductor devices, and thin film transistors (TFTs) are also applicable.
), SOI (Silicon On Insulator), vertical MOS (Ve
vertical MOS) -FET, vertical double diffusion MOS (VDMO)
S; Vertical Double-diffused MOS) -FET, vertical V
Groove MOS (VVMOS; Vertical V-grooved MOS) -F
A channel region near the surface of the body region facing the gate electrode with an insulating film interposed therebetween, such as ET, gallium arsenide FET (GaAs-FET), heterojunction FET (HEMT), and InP-FET. The present invention can be applied to all field effect semiconductor devices in which electric field is induced. Even when the present invention is applied to these field effect semiconductor devices, it is possible to obtain the same effects as those of the above-described embodiments.

Further, although the present invention is applied to the field effect semiconductor device in which the first conductivity type is n type and the second conductivity type is p type, the opposite mode of the first conductivity type is p type. The present invention can be similarly applied to a field effect semiconductor device in which the second conductivity type is n-type. Even in this case, the maximum impurity concentration region that is not affected by the extent of the spread of the source region is surely present, and the same effect as that of the above embodiment can be obtained.

Further, in the above-mentioned field effect type semiconductor device, p ^{+ in} which the conductivity type of the n ⁺ type drain region is changed.
The present invention can be similarly applied to a conductivity modulation type semiconductor device having a drain region of the same type. For example,
Insulated Gate Bipolar Transistor (IGBT)
eGate Bipolar-mode Transistor) is most suitable when the present invention is applied. In this case, the resistance can be reduced while increasing the withstand voltage (punch through voltage).

The field-effect semiconductor device 10 and the like shown in the embodiment need only have a sectional structure as shown in FIGS. 1 and 14 and the like, and the shape of the field-effect semiconductor device 10 and the like viewed from above. I'm not stuck. For example, the shape of the field-effect semiconductor device 10 or the like seen from above may be a lattice shape, a stripe shape, a circular (elliptical) shape, or a polygonal shape such as a triangle or more, which does not affect the present invention.

[0034]

As described above, according to the invention of claim 1, in the channel region facing the gate electrode in the body region, the maximum impurity concentration region is located at a position distant from the region where the source region is in contact with the body region. Since the structure is made to exist, even if the extent of the spread of the source region is changed, the maximum impurity concentration portion is not affected. Therefore, a portion having the highest impurity concentration always exists in the middle of the flow path of electrons flowing through the channel region, and the threshold voltage depending on the highest impurity concentration can be stabilized.

Further, according to the second aspect of the present invention, since the body region forming step of introducing the impurity into the deep portion of the semiconductor substrate from the oblique direction is provided, the introduced impurity is horizontally shifted in the semiconductor substrate. Many are present in the portion along the uneven shape which is almost the same as the uneven shape on the surface.
Therefore, in the channel region of the body region facing the gate electrode, a large amount of impurities are present in a portion horizontally displaced from the vertical wall of the gate electrode, and this is the highest impurity concentration portion. Therefore, even if the extent of the spread of the source region changes, the highest impurity concentration region is not affected, and the threshold voltage depending on the concentration of the highest impurity concentration region can be stabilized.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a structure of a field effect semiconductor device of the present invention.

FIG. 2 is a diagram showing a change in impurity concentration in a channel current direction.

FIG. 3 is a diagram showing a change in impurity concentration in a channel current direction.

FIG. 4 is a diagram showing a step of forming a first insulating film.

FIG. 5 is a diagram showing a step of forming a gate electrode.

FIG. 6 is a diagram showing a step of forming a source region.

FIG. 7 is a diagram showing a step of forming a body region.

FIG. 8 is a diagram showing a method of introducing impurities.

FIG. 9 is a diagram showing a step of forming a second insulating film.

FIG. 10 is a diagram showing a step of etching the first insulating film and the second insulating film into a predetermined pattern.

FIG. 11 is a diagram showing a step of etching a source region.

FIG. 12 is a diagram showing a change in impurity concentration in a channel current direction of a conventional field effect semiconductor device.

FIG. 13 is a diagram showing a change in impurity concentration in the channel current direction.

FIG. 14 is a cross-sectional view showing the structure of a second field effect semiconductor device.

FIG. 15 is a diagram showing a change in impurity concentration in a channel current direction of a second field effect semiconductor device.

FIG. 16 is a cross-sectional view showing a structure of a third field effect semiconductor device.

FIG. 17 is a diagram showing a change in impurity concentration in a channel current direction of a third field effect semiconductor device.

FIG. 18 is a cross-sectional view showing the structure of a conventional field effect semiconductor device.

FIG. 19 is a diagram showing changes in the impurity concentration in the depth direction in the body region of the conventional field effect semiconductor device.

FIG. 20 is a diagram showing a change in impurity concentration in the direction of channel current of a conventional field effect semiconductor device.

FIG. 21 is a diagram showing a change in impurity concentration in the direction of channel current of a conventional field effect semiconductor device.

[Explanation of symbols]

 10 field effect semiconductor device 12 source electrode 14 insulating film 16 gate electrode 18 insulating film (insulating layer) 20 drift region 22 drain region 24 drain electrode 26 source region 28 highest impurity concentration site 30B body region 30C channel region

Claims (2)

[Claims] 1. A body region of a second conductivity type, which is interposed between a source region and a drain region of the first conductivity type and has a conductivity type opposite to the first conductivity type, and a body region of the second conductivity type. In a field effect semiconductor device having a gate electrode facing each other with an insulating layer in between, the highest impurity concentration region in the channel region facing the gate electrode in the body region, the body region in the source region A field-effect-type semiconductor device, characterized in that the field-effect semiconductor device is present at a position away from a contacting portion. 2. A gate electrode forming step of forming a gate electrode on the surface of a semiconductor substrate of the first conductivity type with an insulating layer therebetween, and an impurity is introduced into a shallow portion of the semiconductor substrate in the gate electrode forming step. A source region forming step of forming the first conductive type source region, and an impurity is introduced into a deep portion of the semiconductor substrate from an oblique direction with respect to a surface of the semiconductor substrate on which the gate electrode is formed in the gate electrode forming step. A body region forming step of activating and then forming a body region of a second conductivity type which is a conductivity type opposite to the first conductivity type, and a method of manufacturing a field effect semiconductor device.