FR2400728A1 - Montage pour realiser des corrections pour des operations d'addition ou de soustraction avec des operandes non hexadecimaux dans des unites hexadecimales - Google Patents
Montage pour realiser des corrections pour des operations d'addition ou de soustraction avec des operandes non hexadecimaux dans des unites hexadecimalesInfo
- Publication number
- FR2400728A1 FR2400728A1 FR7823750A FR7823750A FR2400728A1 FR 2400728 A1 FR2400728 A1 FR 2400728A1 FR 7823750 A FR7823750 A FR 7823750A FR 7823750 A FR7823750 A FR 7823750A FR 2400728 A1 FR2400728 A1 FR 2400728A1
- Authority
- FR
- France
- Prior art keywords
- hexadecimal
- assembly
- addition
- operands
- subtraction operations
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/491—Computations with decimal numbers radix 12 or 20.
- G06F7/492—Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination
- G06F7/493—Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination the representation being the natural binary coded representation, i.e. 8421-code
- G06F7/494—Adding; Subtracting
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/49—Computations with a radix, other than binary, 8, 16 or decimal, e.g. ternary, negative or imaginary radices, mixed radix non-linear PCM
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/492—Indexing scheme relating to groups G06F7/492 - G06F7/496
- G06F2207/4921—Single digit adding or subtracting
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/492—Indexing scheme relating to groups G06F7/492 - G06F7/496
- G06F2207/4924—Digit-parallel adding or subtracting
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computing Systems (AREA)
- Computational Mathematics (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Mathematical Analysis (AREA)
- General Engineering & Computer Science (AREA)
- Nonlinear Science (AREA)
- Executing Machine-Instructions (AREA)
- Complex Calculations (AREA)
- Advance Control (AREA)
Abstract
L'invention concerne un montage pour réaliser des corrections pour des opérations d'addition ou de soustraction avec des opérandes non hexadécimaux dans des unités de calcul hexadécimales. Dans ce montage comportant un additionneur complet 1, un registre 10 de memorisation du report est accouplé par un circuit de couplage 20, à la sortie 6 du report de l'additionneur 1 et à sa sortie 12, et par un circuit de couplage 30 à un dispositif délivrant un opérande ou un facteur correctif, à l'autre entrée d'opérandes 3 de l'additionneur 1, les deux circuits 20 et 30 pouvant être raccordés à des entrées de commande respectives 23 et 35, conformément à trois états de commutation possibles. Application notamment aux processeurs de traitement de donnees.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE2737483A DE2737483C3 (de) | 1977-08-19 | 1977-08-19 | Korrektur-Schaltungsanordnung für Additions- oder Substraktionsoperationen mit nicht-hexadezimalen Operanden in hexadezimalen Rechenwerken |
Publications (1)
Publication Number | Publication Date |
---|---|
FR2400728A1 true FR2400728A1 (fr) | 1979-03-16 |
Family
ID=6016831
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR7823750A Withdrawn FR2400728A1 (fr) | 1977-08-19 | 1978-08-11 | Montage pour realiser des corrections pour des operations d'addition ou de soustraction avec des operandes non hexadecimaux dans des unites hexadecimales |
Country Status (5)
Country | Link |
---|---|
US (1) | US4197587A (fr) |
JP (1) | JPS5443640A (fr) |
DE (1) | DE2737483C3 (fr) |
FR (1) | FR2400728A1 (fr) |
GB (1) | GB2003303B (fr) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0303126A1 (fr) * | 1987-08-11 | 1989-02-15 | Siemens Aktiengesellschaft | Dispositif de circuit comportant un étage de comptage à déroulement cyclique suivi d'un étage convertisseur |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4718033A (en) * | 1985-06-28 | 1988-01-05 | Hewlett-Packard Company | Intermediate decimal correction for sequential addition |
US6546410B1 (en) * | 1999-11-16 | 2003-04-08 | Advanced Micro Devices, Inc. | High-speed hexadecimal adding method and system |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2151477A5 (fr) * | 1971-08-30 | 1973-04-20 | Burroughs Corp | |
GB1344080A (en) * | 1971-03-19 | 1974-01-16 | Pico Electronics Ltd | Arithmetic arrangements |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3508037A (en) * | 1967-01-30 | 1970-04-21 | Sperry Rand Corp | Decimal add/subtract circuitry |
US3584206A (en) * | 1968-02-29 | 1971-06-08 | Gen Electric | Serial bcd adder/subtracter/complementer utilizing interlaced data |
US3937941A (en) * | 1974-11-27 | 1976-02-10 | Signetics Corporation | Method and apparatus for packed BCD sign arithmetic employing a two's complement binary adder |
US3958112A (en) * | 1975-05-09 | 1976-05-18 | Honeywell Information Systems, Inc. | Current mode binary/bcd arithmetic array |
-
1977
- 1977-08-19 DE DE2737483A patent/DE2737483C3/de not_active Expired
-
1978
- 1978-08-07 US US05/931,476 patent/US4197587A/en not_active Expired - Lifetime
- 1978-08-11 FR FR7823750A patent/FR2400728A1/fr not_active Withdrawn
- 1978-08-18 GB GB7833896A patent/GB2003303B/en not_active Expired
- 1978-08-18 JP JP10083778A patent/JPS5443640A/ja active Granted
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB1344080A (en) * | 1971-03-19 | 1974-01-16 | Pico Electronics Ltd | Arithmetic arrangements |
FR2151477A5 (fr) * | 1971-08-30 | 1973-04-20 | Burroughs Corp |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0303126A1 (fr) * | 1987-08-11 | 1989-02-15 | Siemens Aktiengesellschaft | Dispositif de circuit comportant un étage de comptage à déroulement cyclique suivi d'un étage convertisseur |
Also Published As
Publication number | Publication date |
---|---|
DE2737483A1 (de) | 1979-02-22 |
JPS5443640A (en) | 1979-04-06 |
DE2737483C3 (de) | 1980-07-03 |
GB2003303A (en) | 1979-03-07 |
JPS5640376B2 (fr) | 1981-09-19 |
GB2003303B (en) | 1982-04-15 |
DE2737483B2 (de) | 1979-10-04 |
US4197587A (en) | 1980-04-08 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |