FR2400728A1 - Montage pour realiser des corrections pour des operations d'addition ou de soustraction avec des operandes non hexadecimaux dans des unites hexadecimales - Google Patents

Montage pour realiser des corrections pour des operations d'addition ou de soustraction avec des operandes non hexadecimaux dans des unites hexadecimales

Info

Publication number
FR2400728A1
FR2400728A1 FR7823750A FR7823750A FR2400728A1 FR 2400728 A1 FR2400728 A1 FR 2400728A1 FR 7823750 A FR7823750 A FR 7823750A FR 7823750 A FR7823750 A FR 7823750A FR 2400728 A1 FR2400728 A1 FR 2400728A1
Authority
FR
France
Prior art keywords
hexadecimal
assembly
addition
operands
subtraction operations
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
FR7823750A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Publication of FR2400728A1 publication Critical patent/FR2400728A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/491Computations with decimal numbers radix 12 or 20.
    • G06F7/492Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination
    • G06F7/493Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination the representation being the natural binary coded representation, i.e. 8421-code
    • G06F7/494Adding; Subtracting
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/49Computations with a radix, other than binary, 8, 16 or decimal, e.g. ternary, negative or imaginary radices, mixed radix non-linear PCM
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/492Indexing scheme relating to groups G06F7/492 - G06F7/496
    • G06F2207/4921Single digit adding or subtracting
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/492Indexing scheme relating to groups G06F7/492 - G06F7/496
    • G06F2207/4924Digit-parallel adding or subtracting

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computational Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Nonlinear Science (AREA)
  • Executing Machine-Instructions (AREA)
  • Advance Control (AREA)
  • Complex Calculations (AREA)

Abstract

L'invention concerne un montage pour réaliser des corrections pour des opérations d'addition ou de soustraction avec des opérandes non hexadécimaux dans des unités de calcul hexadécimales. Dans ce montage comportant un additionneur complet 1, un registre 10 de memorisation du report est accouplé par un circuit de couplage 20, à la sortie 6 du report de l'additionneur 1 et à sa sortie 12, et par un circuit de couplage 30 à un dispositif délivrant un opérande ou un facteur correctif, à l'autre entrée d'opérandes 3 de l'additionneur 1, les deux circuits 20 et 30 pouvant être raccordés à des entrées de commande respectives 23 et 35, conformément à trois états de commutation possibles. Application notamment aux processeurs de traitement de donnees.
FR7823750A 1977-08-19 1978-08-11 Montage pour realiser des corrections pour des operations d'addition ou de soustraction avec des operandes non hexadecimaux dans des unites hexadecimales Withdrawn FR2400728A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE2737483A DE2737483C3 (de) 1977-08-19 1977-08-19 Korrektur-Schaltungsanordnung für Additions- oder Substraktionsoperationen mit nicht-hexadezimalen Operanden in hexadezimalen Rechenwerken

Publications (1)

Publication Number Publication Date
FR2400728A1 true FR2400728A1 (fr) 1979-03-16

Family

ID=6016831

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7823750A Withdrawn FR2400728A1 (fr) 1977-08-19 1978-08-11 Montage pour realiser des corrections pour des operations d'addition ou de soustraction avec des operandes non hexadecimaux dans des unites hexadecimales

Country Status (5)

Country Link
US (1) US4197587A (fr)
JP (1) JPS5443640A (fr)
DE (1) DE2737483C3 (fr)
FR (1) FR2400728A1 (fr)
GB (1) GB2003303B (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0303126A1 (fr) * 1987-08-11 1989-02-15 Siemens Aktiengesellschaft Dispositif de circuit comportant un étage de comptage à déroulement cyclique suivi d'un étage convertisseur

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4718033A (en) * 1985-06-28 1988-01-05 Hewlett-Packard Company Intermediate decimal correction for sequential addition
US6546410B1 (en) * 1999-11-16 2003-04-08 Advanced Micro Devices, Inc. High-speed hexadecimal adding method and system

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2151477A5 (fr) * 1971-08-30 1973-04-20 Burroughs Corp
GB1344080A (en) * 1971-03-19 1974-01-16 Pico Electronics Ltd Arithmetic arrangements

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3508037A (en) * 1967-01-30 1970-04-21 Sperry Rand Corp Decimal add/subtract circuitry
US3584206A (en) * 1968-02-29 1971-06-08 Gen Electric Serial bcd adder/subtracter/complementer utilizing interlaced data
US3937941A (en) * 1974-11-27 1976-02-10 Signetics Corporation Method and apparatus for packed BCD sign arithmetic employing a two's complement binary adder
US3958112A (en) * 1975-05-09 1976-05-18 Honeywell Information Systems, Inc. Current mode binary/bcd arithmetic array

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1344080A (en) * 1971-03-19 1974-01-16 Pico Electronics Ltd Arithmetic arrangements
FR2151477A5 (fr) * 1971-08-30 1973-04-20 Burroughs Corp

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0303126A1 (fr) * 1987-08-11 1989-02-15 Siemens Aktiengesellschaft Dispositif de circuit comportant un étage de comptage à déroulement cyclique suivi d'un étage convertisseur

Also Published As

Publication number Publication date
US4197587A (en) 1980-04-08
DE2737483B2 (de) 1979-10-04
DE2737483A1 (de) 1979-02-22
GB2003303B (en) 1982-04-15
JPS5640376B2 (fr) 1981-09-19
JPS5443640A (en) 1979-04-06
DE2737483C3 (de) 1980-07-03
GB2003303A (en) 1979-03-07

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Legal Events

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