GB1344080A - Arithmetic arrangements - Google Patents

Arithmetic arrangements

Info

Publication number
GB1344080A
GB1344080A GB1344080DA GB1344080A GB 1344080 A GB1344080 A GB 1344080A GB 1344080D A GB1344080D A GB 1344080DA GB 1344080 A GB1344080 A GB 1344080A
Authority
GB
United Kingdom
Prior art keywords
bcd
binary
sum
add
subtract
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Pico Electronics Ltd
Original Assignee
Pico Electronics Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Pico Electronics Ltd filed Critical Pico Electronics Ltd
Publication of GB1344080A publication Critical patent/GB1344080A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/491—Computations with decimal numbers radix 12 or 20.
    • G06F7/492—Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination
    • G06F7/493—Computations with decimal numbers radix 12 or 20. using a binary weighted representation within each denomination the representation being the natural binary coded representation, i.e. 8421-code
    • G06F7/494—Adding; Subtracting
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/492—Indexing scheme relating to groups G06F7/492 - G06F7/496
    • G06F2207/4921—Single digit adding or subtracting

Landscapes

  • Engineering & Computer Science (AREA)
  • Computing Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Detection And Correction Of Errors (AREA)

Abstract

1344080 BCD addition PICO ELECTRONICS Ltd 19 March 1971 11735/71 Divided out of 1344079 Heading G4A Two BCD numbers are added (or subtracted) using binary adders and means for adding (or subtracting) a six. Two 4 bit BCD numbers X and Y are passed through gates 3 at clock time to a binary add/ subtract unit 1 which can receive a carry digit 4 and an add/subtract command 5. The result and carry appear on lines S and C at times # 3 , # 4 respectively. The sum S is in binary code which will differ from BCD if it is more than 9. To convert the binary to BCD it is therefore necessary to add a six if the sum S is greater than 9 (or subtract for subtraction operations). A number forming means 8 produces an output 6 or 0 depending on input 9 which in turn depends on whether S is greater than 9 or not, and the output of means 8 passes to the adder/ subtractor 8 at the same time as the sum S is returned via gate 11. A second addition/sub. traction occurs and the result appears on lines S, C. In subtraction, a negative number is formed in complement form and is recognized by means of its carry. The adder/subtractor comprises four binary adders (Figs. 2, 3, not shown) and all the circuitry may be formed of IGFET's on a single integrated circuit chip. The circuit may be used in a calculator as described in Specification 1,344,079.
GB1344080D 1971-03-19 1971-03-19 Arithmetic arrangements Expired GB1344080A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB1173571 1971-03-19

Publications (1)

Publication Number Publication Date
GB1344080A true GB1344080A (en) 1974-01-16

Family

ID=9991713

Family Applications (1)

Application Number Title Priority Date Filing Date
GB1344080D Expired GB1344080A (en) 1971-03-19 1971-03-19 Arithmetic arrangements

Country Status (1)

Country Link
GB (1) GB1344080A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2400728A1 (en) * 1977-08-19 1979-03-16 Siemens Ag ASSEMBLY TO MAKE CORRECTIONS FOR ADDITION OR SUBTRACTION OPERATIONS WITH NON-HEXADECIMAL OPERANDS IN HEXADECIMAL UNITS

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2400728A1 (en) * 1977-08-19 1979-03-16 Siemens Ag ASSEMBLY TO MAKE CORRECTIONS FOR ADDITION OR SUBTRACTION OPERATIONS WITH NON-HEXADECIMAL OPERANDS IN HEXADECIMAL UNITS

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Legal Events

Date Code Title Description
PS Patent sealed
PCNP Patent ceased through non-payment of renewal fee