GB1181725A - Improvements relating to Calculating Apparatus - Google Patents

Improvements relating to Calculating Apparatus

Info

Publication number
GB1181725A
GB1181725A GB3091367A GB3091367A GB1181725A GB 1181725 A GB1181725 A GB 1181725A GB 3091367 A GB3091367 A GB 3091367A GB 3091367 A GB3091367 A GB 3091367A GB 1181725 A GB1181725 A GB 1181725A
Authority
GB
United Kingdom
Prior art keywords
signals
group
generate
stages
logic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB3091367A
Inventor
Peter Michael Melliar-Smith
Neil David Gammage
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Allard Way Holdings Ltd
Original Assignee
Elliott Brothers London Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Elliott Brothers London Ltd filed Critical Elliott Brothers London Ltd
Priority to GB3091367A priority Critical patent/GB1181725A/en
Priority to FR1578216D priority patent/FR1578216A/fr
Publication of GB1181725A publication Critical patent/GB1181725A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
    • G06F7/508—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages using carry look-ahead circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
    • G06F7/507—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages using selection between two conditionally calculated carry or sum values
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
    • H03K19/09441—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET of the same canal type

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Optimization (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Complex Calculations (AREA)

Abstract

1,181,725. Adder arrangements. ELLIOTT BROS. (LONDON) Ltd. 3 July, 1968 [5 July. 1967], No. 30913/67. Heading G4A. A fast parallel binary adder comprises a series of stages (one for each corresponding pair of bits to be added) arranged in multistage groups which operate at two time-separated levels of logic, the first level being concerned with generating from corresponding pairs of binary bits signals representing first and second half sums, stage carry generate, stage carry propagate, group carry generate and group carry propagate, the second level being concerned with deriving sum outputs from the output signals of the first level taking into account any carry. The first level of logic for the first two stages of an embodiment in which each group comprises two stages is shown in Fig. 3. In logic block 10 signals A 1 and B 1 representing the first corresponding pair of bits to be added are used to generate stage carry propagate P and stage carry generate G signals in true and inverted form together with first and second half sum signals S 01 and S 11 . In logic block 11, the second pair of bit signals A 2 , B 2 are used to generate the half sum signals S 02 and S 12 only. Group generate GG and group propagate GP signals in true and inverted form are generated in blocks 12 and 13 from the same input signals. The second level of logic for stages 1 and 2 is shown in blocks 15 and 16 of Fig. 5, where the output signals of blocks 10 and 11 together with a control signal Co in true and inverted form are used to generate sum outputs S 1 and S 2 for the first two stages. The control signal Co is binary 1 for addition and 0 for subtraction. The group carry generate and group carry propagate signals from blocks 12 and 13 are used in blocks 17 and 18 which correspond to the second level of logic for stages 3 and 4 (i.e. the next group in the series). Generalized equations for the sum outputs for any stage are derived in the Specification, the only signals carried forward from one group to later groups in the series being the group carry generate and group carry propagate signals. The gates of the logic blocks may be formed of metal oxide silicon transistors (MOST's) using integrated circuit techniques.
GB3091367A 1967-07-05 1967-07-05 Improvements relating to Calculating Apparatus Expired GB1181725A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
GB3091367A GB1181725A (en) 1967-07-05 1967-07-05 Improvements relating to Calculating Apparatus
FR1578216D FR1578216A (en) 1967-07-05 1968-07-04

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB3091367A GB1181725A (en) 1967-07-05 1967-07-05 Improvements relating to Calculating Apparatus

Publications (1)

Publication Number Publication Date
GB1181725A true GB1181725A (en) 1970-02-18

Family

ID=10315040

Family Applications (1)

Application Number Title Priority Date Filing Date
GB3091367A Expired GB1181725A (en) 1967-07-05 1967-07-05 Improvements relating to Calculating Apparatus

Country Status (2)

Country Link
FR (1) FR1578216A (en)
GB (1) GB1181725A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2184579A (en) * 1985-12-20 1987-06-24 Texas Instruments Ltd A multi-stage parallel binary adder

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2184579A (en) * 1985-12-20 1987-06-24 Texas Instruments Ltd A multi-stage parallel binary adder
GB2184579B (en) * 1985-12-20 1989-10-25 Texas Instruments Ltd A multi-stage parallel binary adder

Also Published As

Publication number Publication date
FR1578216A (en) 1969-08-14

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