FR2371017A1 - Systeme de traitement d'entree/sortie utilisant des processeurs verrouilles - Google Patents

Systeme de traitement d'entree/sortie utilisant des processeurs verrouilles

Info

Publication number
FR2371017A1
FR2371017A1 FR7734198A FR7734198A FR2371017A1 FR 2371017 A1 FR2371017 A1 FR 2371017A1 FR 7734198 A FR7734198 A FR 7734198A FR 7734198 A FR7734198 A FR 7734198A FR 2371017 A1 FR2371017 A1 FR 2371017A1
Authority
FR
France
Prior art keywords
input
signals
output processing
output
processing system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7734198A
Other languages
English (en)
Other versions
FR2371017B1 (fr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull HN Information Systems Italia SpA
Bull HN Information Systems Inc
Original Assignee
Honeywell Information Systems Italia SpA
Honeywell Information Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Information Systems Italia SpA, Honeywell Information Systems Inc filed Critical Honeywell Information Systems Italia SpA
Publication of FR2371017A1 publication Critical patent/FR2371017A1/fr
Application granted granted Critical
Publication of FR2371017B1 publication Critical patent/FR2371017B1/fr
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1629—Error detection by comparing the output of redundant processing systems
    • G06F11/1641—Error detection by comparing the output of redundant processing systems where the comparison is not performed by the redundant processing components
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0745—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in an input/output transactions management context
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/079—Root cause analysis, i.e. error or fault diagnosis
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1629—Error detection by comparing the output of redundant processing systems
    • G06F11/165—Error detection by comparing the output of redundant processing systems with continued operation after detection of the error
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/2053—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where persistent mass storage functionality or persistent mass storage control functionality is redundant
    • G06F11/2089—Redundant storage control functionality
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Biomedical Technology (AREA)
  • Hardware Redundancy (AREA)
  • Multi Processors (AREA)
  • Debugging And Monitoring (AREA)

Abstract

L'invention concerne un système de traitement d'entrée/sortie. Ce système comprend plusieurs modules qui comportent des moyens pour générer des signaux de sortie et pour recevoir des signaux d'entrée, et une interface de système qui comporte des registres pour désigner différentes configurations des différentes unités d'entrée/sortie, des circuits de comparaison reliés aux bornes d'interface de chacune des différentes unités de traitement d'entrée/sortie, ces circuits de comparaison servant à générer des signaux représentant un défaut de comparaison entre les séries de signaux de sortie, et un moyen de séquence agissant en réponse desdits signaux de défaut de comparaison. Application aux systèmes comportant des unités en double.
FR7734198A 1976-11-15 1977-11-14 Systeme de traitement d'entree/sortie utilisant des processeurs verrouilles Granted FR2371017A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/741,632 US4099234A (en) 1976-11-15 1976-11-15 Input/output processing system utilizing locked processors

Publications (2)

Publication Number Publication Date
FR2371017A1 true FR2371017A1 (fr) 1978-06-09
FR2371017B1 FR2371017B1 (fr) 1985-01-18

Family

ID=24981524

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7734198A Granted FR2371017A1 (fr) 1976-11-15 1977-11-14 Systeme de traitement d'entree/sortie utilisant des processeurs verrouilles

Country Status (9)

Country Link
US (1) US4099234A (fr)
JP (1) JPS5391542A (fr)
AU (1) AU510225B2 (fr)
CA (1) CA1109563A (fr)
DE (1) DE2750299A1 (fr)
FR (1) FR2371017A1 (fr)
GB (1) GB1595919A (fr)
IT (1) IT1090438B (fr)
NL (1) NL7712493A (fr)

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EP0182134A2 (fr) * 1984-11-20 1986-05-28 Siemens Aktiengesellschaft Méthode de mise en oeuvre d'un système multicalculateurs à sécurité intrinsèque comportant plusieur circuits inprimés d'entrées/sorties à sécurité non intrinsèque

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US5185877A (en) * 1987-09-04 1993-02-09 Digital Equipment Corporation Protocol for transfer of DMA data
EP0306211A3 (fr) * 1987-09-04 1990-09-26 Digital Equipment Corporation Système synchronisé à double calculateur
EP0325078B1 (fr) * 1988-01-22 1992-09-09 International Business Machines Corporation Mécanisme de détection et de signalisation d'erreur sur un bus synchrone
WO1989008883A1 (fr) * 1988-03-14 1989-09-21 Unisys Corporation Processeur de verrouillage au niveau enregistrement pour systeme de donnees de multitraitement
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US5189665A (en) * 1989-03-30 1993-02-23 Texas Instruments Incorporated Programmable configurable digital crossbar switch
US5369749A (en) * 1989-05-17 1994-11-29 Ibm Corporation Method and apparatus for the direct transfer of information between application programs running on distinct processors without utilizing the services of one or both operating systems
US5155809A (en) * 1989-05-17 1992-10-13 International Business Machines Corp. Uncoupling a central processing unit from its associated hardware for interaction with data handling apparatus alien to the operating system controlling said unit and hardware
US5369767A (en) * 1989-05-17 1994-11-29 International Business Machines Corp. Servicing interrupt requests in a data processing system without using the services of an operating system
US5325517A (en) * 1989-05-17 1994-06-28 International Business Machines Corporation Fault tolerant data processing system
US5113522A (en) * 1989-05-17 1992-05-12 International Business Machines Corporation Data processing system with system resource management for itself and for an associated alien processor
US5144692A (en) * 1989-05-17 1992-09-01 International Business Machines Corporation System for controlling access by first system to portion of main memory dedicated exclusively to second system to facilitate input/output processing via first system
US5283868A (en) * 1989-05-17 1994-02-01 International Business Machines Corp. Providing additional system characteristics to a data processing system through operations of an application program, transparently to the operating system
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US7065672B2 (en) 2001-03-28 2006-06-20 Stratus Technologies Bermuda Ltd. Apparatus and methods for fault-tolerant computing using a switching fabric
US6971043B2 (en) * 2001-04-11 2005-11-29 Stratus Technologies Bermuda Ltd Apparatus and method for accessing a mass storage device in a fault-tolerant server
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FR2862457B1 (fr) * 2003-11-13 2006-02-24 Arteris Systeme et procede de transmission d'une sequence de messages dans un reseau d'interconnexions.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0182134A2 (fr) * 1984-11-20 1986-05-28 Siemens Aktiengesellschaft Méthode de mise en oeuvre d'un système multicalculateurs à sécurité intrinsèque comportant plusieur circuits inprimés d'entrées/sorties à sécurité non intrinsèque
EP0182134A3 (en) * 1984-11-20 1988-07-20 Siemens Aktiengesellschaft Berlin Und Munchen Method for operating a technically with signal-secure multi-computer system with technically signal-insecure input-output units

Also Published As

Publication number Publication date
AU3025677A (en) 1979-05-10
US4099234A (en) 1978-07-04
CA1109563A (fr) 1981-09-22
NL7712493A (nl) 1978-05-17
JPS62538B2 (fr) 1987-01-08
JPS5391542A (en) 1978-08-11
DE2750299A1 (de) 1978-05-18
GB1595919A (en) 1981-08-19
AU510225B2 (en) 1980-06-12
IT1090438B (it) 1985-06-26
FR2371017B1 (fr) 1985-01-18

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