FR2349175A1 - Systeme de traitement de donnees utilisant une instruction generale - Google Patents
Systeme de traitement de donnees utilisant une instruction generaleInfo
- Publication number
- FR2349175A1 FR2349175A1 FR7705183A FR7705183A FR2349175A1 FR 2349175 A1 FR2349175 A1 FR 2349175A1 FR 7705183 A FR7705183 A FR 7705183A FR 7705183 A FR7705183 A FR 7705183A FR 2349175 A1 FR2349175 A1 FR 2349175A1
- Authority
- FR
- France
- Prior art keywords
- data processing
- processing system
- general instruction
- instruction
- general
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
- G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
- G06F9/325—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for loops, e.g. loop detection or loop counter
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Executing Machine-Instructions (AREA)
- Advance Control (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US05/679,583 US4037213A (en) | 1976-04-23 | 1976-04-23 | Data processor using a four section instruction format for control of multi-operation functions by a single instruction |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2349175A1 true FR2349175A1 (fr) | 1977-11-18 |
FR2349175B1 FR2349175B1 (fr) | 1979-03-09 |
Family
ID=24727488
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR7705183A Granted FR2349175A1 (fr) | 1976-04-23 | 1977-02-18 | Systeme de traitement de donnees utilisant une instruction generale |
Country Status (4)
Country | Link |
---|---|
US (1) | US4037213A (fr) |
JP (1) | JPS52129344A (fr) |
DE (1) | DE2718110A1 (fr) |
FR (1) | FR2349175A1 (fr) |
Families Citing this family (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4133028A (en) * | 1976-10-01 | 1979-01-02 | Data General Corporation | Data processing system having a cpu register file and a memory address register separate therefrom |
US4285035A (en) * | 1979-01-02 | 1981-08-18 | Honeywell Information Systems Inc. | Apparatus and method for rewrite data insertion in a three descriptor instruction |
US4292667A (en) * | 1979-06-27 | 1981-09-29 | Burroughs Corporation | Microprocessor system facilitating repetition of instructions |
US4379328A (en) * | 1979-06-27 | 1983-04-05 | Burroughs Corporation | Linear sequencing microprocessor facilitating |
US4516218A (en) * | 1980-06-26 | 1985-05-07 | Texas Instruments Incorporated | Memory system with single command selective sequential accessing of predetermined pluralities of data locations |
US4462074A (en) * | 1981-11-19 | 1984-07-24 | Codex Corporation | Do loop circuit |
US4724517A (en) * | 1982-11-26 | 1988-02-09 | Inmos Limited | Microcomputer with prefixing functions |
US4604695A (en) * | 1983-09-30 | 1986-08-05 | Honeywell Information Systems Inc. | Nibble and word addressable memory arrangement |
JP2675779B2 (ja) * | 1987-01-12 | 1997-11-12 | 沖電気工業株式会社 | 命令解読装置 |
US5276819A (en) * | 1987-05-01 | 1994-01-04 | Hewlett-Packard Company | Horizontal computer having register multiconnect for operand address generation during execution of iterations of a loop of program code |
US5036454A (en) * | 1987-05-01 | 1991-07-30 | Hewlett-Packard Company | Horizontal computer having register multiconnect for execution of a loop with overlapped code |
US5083267A (en) * | 1987-05-01 | 1992-01-21 | Hewlett-Packard Company | Horizontal computer having register multiconnect for execution of an instruction loop with recurrance |
US5226128A (en) * | 1987-05-01 | 1993-07-06 | Hewlett-Packard Company | Horizontal computer having register multiconnect for execution of a loop with a branch |
US5307474A (en) * | 1987-09-30 | 1994-04-26 | Mitsubishi Denki Kabushiki Kaisha | Apparatus and method for processing literal operand computer instructions |
US5261113A (en) * | 1988-01-25 | 1993-11-09 | Digital Equipment Corporation | Apparatus and method for single operand register array for vector and scalar data processing operations |
US5155820A (en) * | 1989-02-21 | 1992-10-13 | Gibson Glenn A | Instruction format with designations for operand lengths of byte, half word, word, or double word encoded in address bits |
EP0389175A3 (fr) * | 1989-03-15 | 1992-11-19 | Fujitsu Limited | Système de préextraction de données |
US5179691A (en) * | 1989-04-12 | 1993-01-12 | Unisys Corporation | N-byte stack-oriented CPU using a byte-selecting control for enhancing a dual-operation with an M-byte instruction word user program where M<N<2M |
US5121502A (en) * | 1989-12-20 | 1992-06-09 | Hewlett-Packard Company | System for selectively communicating instructions from memory locations simultaneously or from the same memory locations sequentially to plurality of processing |
US5168571A (en) * | 1990-01-24 | 1992-12-01 | International Business Machines Corporation | System for aligning bytes of variable multi-bytes length operand based on alu byte length and a number of unprocessed byte data |
JPH04156613A (ja) * | 1990-10-20 | 1992-05-29 | Fujitsu Ltd | 命令バッファ装置 |
US5859991A (en) * | 1995-06-07 | 1999-01-12 | Advanced Micro Devices, Inc. | Parallel and scalable method for identifying valid instructions and a superscalar microprocessor including an instruction scanning unit employing the method |
US5852727A (en) * | 1997-03-10 | 1998-12-22 | Advanced Micro Devices, Inc. | Instruction scanning unit for locating instructions via parallel scanning of start and end byte information |
FR2770659A1 (fr) | 1997-10-31 | 1999-05-07 | Sgs Thomson Microelectronics | Processeur de traitement perfectionne |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB942153A (en) * | 1961-01-26 | 1963-11-20 | Int Computers & Tabulators Ltd | Improvements in or relating to data processing apparatus |
US3331056A (en) * | 1964-07-15 | 1967-07-11 | Honeywell Inc | Variable width addressing arrangement |
US3343138A (en) * | 1964-10-07 | 1967-09-19 | Bell Telephone Labor Inc | Data processor employing double indexing |
US3522589A (en) * | 1968-10-31 | 1970-08-04 | Honeywell Inc | Data processing apparatus |
JPS5224364B2 (fr) * | 1972-12-01 | 1977-06-30 | ||
DE2309029C2 (de) * | 1973-02-23 | 1985-10-03 | Nixdorf Computer Ag, 4790 Paderborn | Elektronische Digital-Datenverarbeitungs-Anlage mit Mikroprogrammsteuerung |
JPS50116247A (fr) * | 1974-02-28 | 1975-09-11 |
-
1976
- 1976-04-23 US US05/679,583 patent/US4037213A/en not_active Expired - Lifetime
-
1977
- 1977-02-18 FR FR7705183A patent/FR2349175A1/fr active Granted
- 1977-03-09 JP JP2496377A patent/JPS52129344A/ja active Pending
- 1977-04-22 DE DE19772718110 patent/DE2718110A1/de not_active Withdrawn
Also Published As
Publication number | Publication date |
---|---|
FR2349175B1 (fr) | 1979-03-09 |
DE2718110A1 (de) | 1977-11-10 |
JPS52129344A (en) | 1977-10-29 |
US4037213A (en) | 1977-07-19 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |