FR2337402B1 - - Google Patents

Info

Publication number
FR2337402B1
FR2337402B1 FR7635304A FR7635304A FR2337402B1 FR 2337402 B1 FR2337402 B1 FR 2337402B1 FR 7635304 A FR7635304 A FR 7635304A FR 7635304 A FR7635304 A FR 7635304A FR 2337402 B1 FR2337402 B1 FR 2337402B1
Authority
FR
France
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR7635304A
Other versions
FR2337402A1 (fr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of FR2337402A1 publication Critical patent/FR2337402A1/fr
Application granted granted Critical
Publication of FR2337402B1 publication Critical patent/FR2337402B1/fr
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66833Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/04Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107Substrate region of field-effect devices
    • H01L29/1075Substrate region of field-effect devices of field-effect transistors
    • H01L29/1079Substrate region of field-effect devices of field-effect transistors with insulated gate
    • H01L29/1083Substrate region of field-effect devices of field-effect transistors with insulated gate with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/792Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
FR7635304A 1975-12-31 1976-11-19 Dispositif semi-conducteur du genre metal-nitrure-oxyde, semi-conducteur utilise en tant qu'element de memoire Granted FR2337402A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/645,770 US4017888A (en) 1975-12-31 1975-12-31 Non-volatile metal nitride oxide semiconductor device

Publications (2)

Publication Number Publication Date
FR2337402A1 FR2337402A1 (fr) 1977-07-29
FR2337402B1 true FR2337402B1 (fr) 1980-10-24

Family

ID=24590415

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7635304A Granted FR2337402A1 (fr) 1975-12-31 1976-11-19 Dispositif semi-conducteur du genre metal-nitrure-oxyde, semi-conducteur utilise en tant qu'element de memoire

Country Status (5)

Country Link
US (1) US4017888A (fr)
JP (1) JPS5283183A (fr)
DE (1) DE2657643A1 (fr)
FR (1) FR2337402A1 (fr)
GB (1) GB1502587A (fr)

Families Citing this family (80)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4108686A (en) * 1977-07-22 1978-08-22 Rca Corp. Method of making an insulated gate field effect transistor by implanted double counterdoping
US4173766A (en) * 1977-09-16 1979-11-06 Fairchild Camera And Instrument Corporation Insulated gate field-effect transistor read-only memory cell
US4350991A (en) * 1978-01-06 1982-09-21 International Business Machines Corp. Narrow channel length MOS field effect transistor with field protection region for reduced source-to-substrate capacitance
US4250206A (en) * 1978-12-11 1981-02-10 Texas Instruments Incorporated Method of making non-volatile semiconductor memory elements
US4353083A (en) * 1978-11-27 1982-10-05 Ncr Corporation Low voltage nonvolatile memory device
JPS55500965A (fr) * 1978-11-27 1980-11-13
DE3018988A1 (de) * 1980-05-17 1981-11-26 Deutsche Itt Industries Gmbh, 7800 Freiburg Isolierschicht-feldeffekttransistor
GB2089566B (en) * 1980-12-11 1985-07-24 Gen Instrument Corp Electrically alterable read only memory semiconductor device
US4521796A (en) * 1980-12-11 1985-06-04 General Instrument Corporation Memory implant profile for improved channel shielding in electrically alterable read only memory semiconductor device
JPS5833870A (ja) * 1981-08-24 1983-02-28 Hitachi Ltd 半導体装置
FR2569054B1 (fr) * 1984-08-10 1986-11-28 Eurotechnique Sa Dispositif de neutralisation de l'acces a une zone a proteger d'un circuit integre
JPH0315792Y2 (fr) * 1985-01-17 1991-04-05
US4979005A (en) * 1986-07-23 1990-12-18 Texas Instruments Incorporated Floating-gate memory cell with tailored doping profile
US5156990A (en) * 1986-07-23 1992-10-20 Texas Instruments Incorporated Floating-gate memory cell with tailored doping profile
US5036375A (en) * 1986-07-23 1991-07-30 Texas Instruments Incorporated Floating-gate memory cell with tailored doping profile
EP0311816A1 (fr) * 1987-10-15 1989-04-19 BBC Brown Boveri AG Elément semi-conducteur et méthode de fabrication
IT1227821B (it) * 1988-12-29 1991-05-07 Sgs Thomson Microelectronics Struttura di catena di contatti per il controllo della difettosita' di circuiti di memorie eprom
US5393683A (en) * 1992-05-26 1995-02-28 Micron Technology, Inc. Method of making semiconductor devices having two-layer gate structure
KR100354406B1 (ko) * 1992-11-02 2002-12-26 엔브이엑스코포레이션 플래시메모리장치,및이의제조및사용방법
US5622880A (en) * 1994-08-18 1997-04-22 Sun Microsystems, Inc. Method of making a low power, high performance junction transistor
US6297096B1 (en) * 1997-06-11 2001-10-02 Saifun Semiconductors Ltd. NROM fabrication method
IL125604A (en) 1997-07-30 2004-03-28 Saifun Semiconductors Ltd Non-volatile electrically erasable and programmble semiconductor memory cell utilizing asymmetrical charge
US6768165B1 (en) 1997-08-01 2004-07-27 Saifun Semiconductors Ltd. Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping
US6633496B2 (en) 1997-12-12 2003-10-14 Saifun Semiconductors Ltd. Symmetric architecture for memory cells having widely spread metal bit lines
US6430077B1 (en) 1997-12-12 2002-08-06 Saifun Semiconductors Ltd. Method for regulating read voltage level at the drain of a cell in a symmetric array
US6633499B1 (en) 1997-12-12 2003-10-14 Saifun Semiconductors Ltd. Method for reducing voltage drops in symmetric array architectures
US6087208A (en) * 1998-03-31 2000-07-11 Advanced Micro Devices, Inc. Method for increasing gate capacitance by using both high and low dielectric gate material
US6215148B1 (en) 1998-05-20 2001-04-10 Saifun Semiconductors Ltd. NROM cell with improved programming, erasing and cycling
US6348711B1 (en) 1998-05-20 2002-02-19 Saifun Semiconductors Ltd. NROM cell with self-aligned programming and erasure areas
US6429063B1 (en) * 1999-10-26 2002-08-06 Saifun Semiconductors Ltd. NROM cell with generally decoupled primary and secondary injection
US6396368B1 (en) 1999-11-10 2002-05-28 Hrl Laboratories, Llc CMOS-compatible MEM switches and method of making
US6396741B1 (en) * 2000-05-04 2002-05-28 Saifun Semiconductors Ltd. Programming of nonvolatile memory cells
US6490204B2 (en) 2000-05-04 2002-12-03 Saifun Semiconductors Ltd. Programming and erasing methods for a reference cell of an NROM array
US6928001B2 (en) * 2000-12-07 2005-08-09 Saifun Semiconductors Ltd. Programming and erasing methods for a non-volatile memory cell
US7217977B2 (en) * 2004-04-19 2007-05-15 Hrl Laboratories, Llc Covert transformation of transistor properties as a circuit protection method
US6815816B1 (en) 2000-10-25 2004-11-09 Hrl Laboratories, Llc Implanted hidden interconnections in a semiconductor device for preventing reverse engineering
JP3881840B2 (ja) * 2000-11-14 2007-02-14 独立行政法人産業技術総合研究所 半導体装置
US6614692B2 (en) * 2001-01-18 2003-09-02 Saifun Semiconductors Ltd. EEPROM array and method for operation thereof
US7294935B2 (en) * 2001-01-24 2007-11-13 Hrl Laboratories, Llc Integrated circuits protected against reverse engineering and method for fabricating the same using an apparent metal contact line terminating on field oxide
US6791191B2 (en) 2001-01-24 2004-09-14 Hrl Laboratories, Llc Integrated circuits protected against reverse engineering and method for fabricating the same using vias without metal terminations
US6584017B2 (en) 2001-04-05 2003-06-24 Saifun Semiconductors Ltd. Method for programming a reference cell
US6677805B2 (en) * 2001-04-05 2004-01-13 Saifun Semiconductors Ltd. Charge pump stage with body effect minimization
US6636440B2 (en) 2001-04-25 2003-10-21 Saifun Semiconductors Ltd. Method for operation of an EEPROM array, including refresh thereof
US6740942B2 (en) * 2001-06-15 2004-05-25 Hrl Laboratories, Llc. Permanently on transistor implemented using a double polysilicon layer CMOS process with buried contact
US6774413B2 (en) * 2001-06-15 2004-08-10 Hrl Laboratories, Llc Integrated circuit structure with programmable connector/isolator
US6643181B2 (en) 2001-10-24 2003-11-04 Saifun Semiconductors Ltd. Method for erasing a memory cell
US7098107B2 (en) * 2001-11-19 2006-08-29 Saifun Semiconductor Ltd. Protective layer in memory device and method therefor
US6583007B1 (en) * 2001-12-20 2003-06-24 Saifun Semiconductors Ltd. Reducing secondary injection effects
US6885585B2 (en) * 2001-12-20 2005-04-26 Saifun Semiconductors Ltd. NROM NOR array
US6700818B2 (en) 2002-01-31 2004-03-02 Saifun Semiconductors Ltd. Method for operating a memory device
US6897535B2 (en) * 2002-05-14 2005-05-24 Hrl Laboratories, Llc Integrated circuit with reverse engineering protection
US6917544B2 (en) 2002-07-10 2005-07-12 Saifun Semiconductors Ltd. Multiple use memory chip
US6826107B2 (en) * 2002-08-01 2004-11-30 Saifun Semiconductors Ltd. High voltage insertion in flash memory cards
US7049667B2 (en) 2002-09-27 2006-05-23 Hrl Laboratories, Llc Conductive channel pseudo block process and circuit to inhibit reverse engineering
US7136304B2 (en) 2002-10-29 2006-11-14 Saifun Semiconductor Ltd Method, system and circuit for programming a non-volatile memory array
US6979606B2 (en) * 2002-11-22 2005-12-27 Hrl Laboratories, Llc Use of silicon block process step to camouflage a false transistor
AU2003293540A1 (en) * 2002-12-13 2004-07-09 Raytheon Company Integrated circuit modification using well implants
US7178004B2 (en) 2003-01-31 2007-02-13 Yan Polansky Memory array programming circuit and a method for using the circuit
US7142464B2 (en) * 2003-04-29 2006-11-28 Saifun Semiconductors Ltd. Apparatus and methods for multi-level sensing in a memory array
US7123532B2 (en) 2003-09-16 2006-10-17 Saifun Semiconductors Ltd. Operating array cells with matched reference cells
US7242063B1 (en) 2004-06-29 2007-07-10 Hrl Laboratories, Llc Symmetric non-intrusive and covert technique to render a transistor permanently non-operable
US7317633B2 (en) 2004-07-06 2008-01-08 Saifun Semiconductors Ltd Protection of NROM devices from charge damage
US7095655B2 (en) 2004-08-12 2006-08-22 Saifun Semiconductors Ltd. Dynamic matching of signal path and reference path for sensing
US7638850B2 (en) 2004-10-14 2009-12-29 Saifun Semiconductors Ltd. Non-volatile memory structure and method of fabrication
US7535765B2 (en) 2004-12-09 2009-05-19 Saifun Semiconductors Ltd. Non-volatile memory device and method for reading cells
CN1838323A (zh) 2005-01-19 2006-09-27 赛芬半导体有限公司 可预防固定模式编程的方法
US8053812B2 (en) 2005-03-17 2011-11-08 Spansion Israel Ltd Contact in planar NROM technology
US7786512B2 (en) 2005-07-18 2010-08-31 Saifun Semiconductors Ltd. Dense non-volatile memory array and method of fabrication
US7668017B2 (en) 2005-08-17 2010-02-23 Saifun Semiconductors Ltd. Method of erasing non-volatile memory cells
US7221138B2 (en) * 2005-09-27 2007-05-22 Saifun Semiconductors Ltd Method and apparatus for measuring charge pump output current
US20070087503A1 (en) * 2005-10-17 2007-04-19 Saifun Semiconductors, Ltd. Improving NROM device characteristics using adjusted gate work function
US7352627B2 (en) 2006-01-03 2008-04-01 Saifon Semiconductors Ltd. Method, system, and circuit for operating a non-volatile memory array
US7808818B2 (en) 2006-01-12 2010-10-05 Saifun Semiconductors Ltd. Secondary injection for NROM
US8253452B2 (en) 2006-02-21 2012-08-28 Spansion Israel Ltd Circuit and method for powering up an integrated circuit and an integrated circuit utilizing same
US7692961B2 (en) 2006-02-21 2010-04-06 Saifun Semiconductors Ltd. Method, circuit and device for disturb-control of programming nonvolatile memory cells by hot-hole injection (HHI) and by channel hot-electron (CHE) injection
US7760554B2 (en) 2006-02-21 2010-07-20 Saifun Semiconductors Ltd. NROM non-volatile memory and mode of operation
US7638835B2 (en) * 2006-02-28 2009-12-29 Saifun Semiconductors Ltd. Double density NROM with nitride strips (DDNS)
US7701779B2 (en) 2006-04-27 2010-04-20 Sajfun Semiconductors Ltd. Method for programming a reference cell
US7605579B2 (en) 2006-09-18 2009-10-20 Saifun Semiconductors Ltd. Measuring and controlling current consumption and output current of charge pumps
US8168487B2 (en) * 2006-09-28 2012-05-01 Hrl Laboratories, Llc Programmable connection and isolation of active regions in an integrated circuit using ambiguous features to confuse a reverse engineer

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3875567A (en) * 1971-12-29 1975-04-01 Sony Corp Memory circuit using variable threshold level field-effect device
JPS4951879A (fr) * 1972-09-20 1974-05-20
US3867204A (en) * 1973-03-19 1975-02-18 Motorola Inc Manufacture of semiconductor devices
US3943542A (en) * 1974-11-06 1976-03-09 International Business Machines, Corporation High reliability, low leakage, self-aligned silicon gate FET and method of fabricating same

Also Published As

Publication number Publication date
FR2337402A1 (fr) 1977-07-29
JPS5531631B2 (fr) 1980-08-19
DE2657643A1 (de) 1977-07-14
US4017888A (en) 1977-04-12
GB1502587A (en) 1978-03-01
JPS5283183A (en) 1977-07-11

Similar Documents

Publication Publication Date Title
JPS51134130U (fr)
CH604015A5 (fr)
CH599898A5 (fr)
BG22031A1 (fr)
BG22955A1 (fr)
CH581916A5 (fr)
CH588086A5 (fr)
CH588647A5 (fr)
CH588811A5 (fr)
CH589774A5 (fr)
CH590576A5 (fr)
CH592465A5 (fr)
CH592515A5 (fr)
CH593567A5 (fr)
CH594132A5 (fr)
CH595870A5 (fr)
CH596080A5 (fr)
CH596496A5 (fr)
CH604468A5 (fr)
CH597882A5 (fr)
CH598081A5 (fr)
CH598208A5 (fr)
CH598404B5 (fr)
CH598520A5 (fr)
CH598992A5 (fr)

Legal Events

Date Code Title Description
ST Notification of lapse