FR2335045A1 - Procede de commande de la duree de vie des porteurs dans les dispositifs semi-conducteurs et dispositifs en resultant - Google Patents
Procede de commande de la duree de vie des porteurs dans les dispositifs semi-conducteurs et dispositifs en resultantInfo
- Publication number
- FR2335045A1 FR2335045A1 FR7632456A FR7632456A FR2335045A1 FR 2335045 A1 FR2335045 A1 FR 2335045A1 FR 7632456 A FR7632456 A FR 7632456A FR 7632456 A FR7632456 A FR 7632456A FR 2335045 A1 FR2335045 A1 FR 2335045A1
- Authority
- FR
- France
- Prior art keywords
- devices
- lifetime
- carriers
- procedure
- controlling
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P30/00—Ion implantation into wafers, substrates or parts of devices
- H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
- H10P30/202—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
- H10P30/204—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/50—Physical imperfections
- H10D62/53—Physical imperfections the imperfections being within the semiconductor body
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P30/00—Ion implantation into wafers, substrates or parts of devices
- H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
- H10P30/208—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically inactive species
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
- H10P95/40—Treatments of semiconductor bodies to modify their internal properties, e.g. to produce internal imperfections
- H10P95/402—Treatments of semiconductor bodies to modify their internal properties, e.g. to produce internal imperfections of silicon bodies
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
- H10W10/01—Manufacture or treatment
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/01—Manufacture or treatment
- H10W70/02—Manufacture or treatment of conductive package substrates serving as an interconnection, e.g. of metal plates
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US64013775A | 1975-12-12 | 1975-12-12 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| FR2335045A1 true FR2335045A1 (fr) | 1977-07-08 |
| FR2335045B1 FR2335045B1 (https=) | 1979-09-21 |
Family
ID=24566992
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| FR7632456A Granted FR2335045A1 (fr) | 1975-12-12 | 1976-10-18 | Procede de commande de la duree de vie des porteurs dans les dispositifs semi-conducteurs et dispositifs en resultant |
Country Status (5)
| Country | Link |
|---|---|
| JP (1) | JPS5272583A (https=) |
| DE (1) | DE2642206A1 (https=) |
| FR (1) | FR2335045A1 (https=) |
| GB (1) | GB1503249A (https=) |
| IT (1) | IT1123671B (https=) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0030856B1 (en) * | 1979-12-13 | 1984-03-21 | Fujitsu Limited | Charge-pumping semiconductor memory cell comprising a charge-storage region and memory device using such a cell |
| EP0253059A3 (en) * | 1986-03-20 | 1989-09-13 | Hitachi, Ltd. | Process for suppressing the rise of the buried layer of a semiconductor device |
| WO1995006956A1 (en) * | 1993-09-03 | 1995-03-09 | National Semiconductor Corporation | Planar isolation method for use in fabrication of microelectronics |
| WO1996026536A1 (en) * | 1995-02-20 | 1996-08-29 | Rohm Co., Ltd. | Semiconductor apparatus with crystal defects and process for its fabrication |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58143563A (ja) * | 1982-02-22 | 1983-08-26 | Hitachi Ltd | 半導体装置の製造方法 |
| NL8301554A (nl) * | 1982-05-06 | 1983-12-01 | Mitsubishi Electric Corp | Geintegreerde schakeling-inrichting van het cmos-type. |
-
1976
- 1976-09-20 DE DE19762642206 patent/DE2642206A1/de active Pending
- 1976-10-18 FR FR7632456A patent/FR2335045A1/fr active Granted
- 1976-11-09 IT IT29128/76A patent/IT1123671B/it active
- 1976-11-11 JP JP51134744A patent/JPS5272583A/ja active Pending
- 1976-12-06 GB GB50821/76A patent/GB1503249A/en not_active Expired
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0030856B1 (en) * | 1979-12-13 | 1984-03-21 | Fujitsu Limited | Charge-pumping semiconductor memory cell comprising a charge-storage region and memory device using such a cell |
| EP0253059A3 (en) * | 1986-03-20 | 1989-09-13 | Hitachi, Ltd. | Process for suppressing the rise of the buried layer of a semiconductor device |
| WO1995006956A1 (en) * | 1993-09-03 | 1995-03-09 | National Semiconductor Corporation | Planar isolation method for use in fabrication of microelectronics |
| WO1996026536A1 (en) * | 1995-02-20 | 1996-08-29 | Rohm Co., Ltd. | Semiconductor apparatus with crystal defects and process for its fabrication |
Also Published As
| Publication number | Publication date |
|---|---|
| DE2642206A1 (de) | 1977-06-23 |
| GB1503249A (en) | 1978-03-08 |
| FR2335045B1 (https=) | 1979-09-21 |
| JPS5272583A (en) | 1977-06-17 |
| IT1123671B (it) | 1986-04-30 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| ST | Notification of lapse |