FR2330077A1 - Data processing control with priority interrupt - interrupt unit controls peripheral operations in either simplex or multiplex mode - Google Patents
Data processing control with priority interrupt - interrupt unit controls peripheral operations in either simplex or multiplex modeInfo
- Publication number
- FR2330077A1 FR2330077A1 FR7513206A FR7513206A FR2330077A1 FR 2330077 A1 FR2330077 A1 FR 2330077A1 FR 7513206 A FR7513206 A FR 7513206A FR 7513206 A FR7513206 A FR 7513206A FR 2330077 A1 FR2330077 A1 FR 2330077A1
- Authority
- FR
- France
- Prior art keywords
- interrupt
- priority
- simplex
- data processing
- unit controls
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Program initiating; Program switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
- Computer And Data Communications (AREA)
- Multi Processors (AREA)
- Exchange Systems With Centralized Control (AREA)
Abstract
The main memory store of a data processing system is coupled via a main memory coordinator to an input/output processor and a central processor. Both processors are in direct communication with each other and the coordinator. The input/output processor has a large number of outputs coupled to peripheral equipment. The outputs may either operate in simplex or multiplex modes and each has facility for interrupt on a priority basis. The main memory store contains the priority interrupt requirements and the central processor provides the necessary decision making facility. Priority networks linked to the input/output processor operate with multiplexing circuits and a demultiplexer in conjunction with an address register.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19742420763 DE2420763C3 (en) | 1974-04-29 | Data processing system, in particular process computer system |
Publications (1)
Publication Number | Publication Date |
---|---|
FR2330077A1 true FR2330077A1 (en) | 1977-05-27 |
Family
ID=5914272
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR7513206A Withdrawn FR2330077A1 (en) | 1974-04-29 | 1975-04-28 | Data processing control with priority interrupt - interrupt unit controls peripheral operations in either simplex or multiplex mode |
Country Status (1)
Country | Link |
---|---|
FR (1) | FR2330077A1 (en) |
-
1975
- 1975-04-28 FR FR7513206A patent/FR2330077A1/en not_active Withdrawn
Also Published As
Publication number | Publication date |
---|---|
DE2420763A1 (en) | 1975-10-30 |
DE2420763B2 (en) | 1976-09-23 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |