FR2313709A1 - Misalignment correction systems for data processors - has intermediate circuits which are controlled by single counter unit - Google Patents

Misalignment correction systems for data processors - has intermediate circuits which are controlled by single counter unit

Info

Publication number
FR2313709A1
FR2313709A1 FR7443623A FR7443623A FR2313709A1 FR 2313709 A1 FR2313709 A1 FR 2313709A1 FR 7443623 A FR7443623 A FR 7443623A FR 7443623 A FR7443623 A FR 7443623A FR 2313709 A1 FR2313709 A1 FR 2313709A1
Authority
FR
France
Prior art keywords
signals
data
counter
output
circuits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7443623A
Other languages
French (fr)
Other versions
FR2313709B1 (en
Inventor
Joseph E Elliott
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Priority to FR7443623A priority Critical patent/FR2313709A1/en
Publication of FR2313709A1 publication Critical patent/FR2313709A1/en
Application granted granted Critical
Publication of FR2313709B1 publication Critical patent/FR2313709B1/fr
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/08—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations, the intermediate ones not being accessible for either enqueue or dequeue operations, e.g. using a shift register
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/20—Signal processing not specific to the method of recording or reproducing; Circuits therefor for correction of skew for multitrack recording
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0656—Data buffering arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Signal Processing (AREA)
  • Complex Calculations (AREA)

Abstract

The intermediate circuits for numerical signals include a data signal shift register, an increment/decrement counter, data input and output means. The circuits also have devices which respond to the simultaneous appearance of input and output control signals, and which prevent the counter from changing the state of these signals. The shift register has interconnected data shift stages. Each stage has output switching and OR-circuits for receipt of signals from all the switches. The counter includes the given number plus one of stable states of the counting indication signals. One of these states being a reference, the other indicating one of the shift stages. The data input has control elements for providing an input control signal which causes the shift register to shift the signals it contains toward the last stage. The data output has control elements supplying an output control signal to the counter.
FR7443623A 1974-12-31 1974-12-31 Misalignment correction systems for data processors - has intermediate circuits which are controlled by single counter unit Granted FR2313709A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR7443623A FR2313709A1 (en) 1974-12-31 1974-12-31 Misalignment correction systems for data processors - has intermediate circuits which are controlled by single counter unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7443623A FR2313709A1 (en) 1974-12-31 1974-12-31 Misalignment correction systems for data processors - has intermediate circuits which are controlled by single counter unit

Publications (2)

Publication Number Publication Date
FR2313709A1 true FR2313709A1 (en) 1976-12-31
FR2313709B1 FR2313709B1 (en) 1978-05-05

Family

ID=9146936

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7443623A Granted FR2313709A1 (en) 1974-12-31 1974-12-31 Misalignment correction systems for data processors - has intermediate circuits which are controlled by single counter unit

Country Status (1)

Country Link
FR (1) FR2313709A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2400242A1 (en) * 1977-08-08 1979-03-09 Honeywell Inf Systems MULTI-BIT MISALIGNMENT CORRECTION BUFFER

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3851335A (en) * 1973-07-30 1974-11-26 Ibm Buffer systems

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3851335A (en) * 1973-07-30 1974-11-26 Ibm Buffer systems

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2400242A1 (en) * 1977-08-08 1979-03-09 Honeywell Inf Systems MULTI-BIT MISALIGNMENT CORRECTION BUFFER

Also Published As

Publication number Publication date
FR2313709B1 (en) 1978-05-05

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