FR2296966A1 - Circuit logique de comparaison en technologie mos complementaire notamment pour 2x bits - Google Patents
Circuit logique de comparaison en technologie mos complementaire notamment pour 2x bitsInfo
- Publication number
- FR2296966A1 FR2296966A1 FR7443621A FR7443621A FR2296966A1 FR 2296966 A1 FR2296966 A1 FR 2296966A1 FR 7443621 A FR7443621 A FR 7443621A FR 7443621 A FR7443621 A FR 7443621A FR 2296966 A1 FR2296966 A1 FR 2296966A1
- Authority
- FR
- France
- Prior art keywords
- words
- bits
- parity bit
- data bits
- comparator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
- H03K19/0948—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET using CMOS or complementary insulated gate field-effect transistors
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/02—Comparing digital values
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Computing Systems (AREA)
- Computational Mathematics (AREA)
- Computer Hardware Design (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Power Engineering (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR7443621A FR2296966A1 (fr) | 1974-12-31 | 1974-12-31 | Circuit logique de comparaison en technologie mos complementaire notamment pour 2x bits |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FR7443621A FR2296966A1 (fr) | 1974-12-31 | 1974-12-31 | Circuit logique de comparaison en technologie mos complementaire notamment pour 2x bits |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| FR2296966A1 true FR2296966A1 (fr) | 1976-07-30 |
| FR2296966B1 FR2296966B1 (enExample) | 1977-07-08 |
Family
ID=9146934
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| FR7443621A Granted FR2296966A1 (fr) | 1974-12-31 | 1974-12-31 | Circuit logique de comparaison en technologie mos complementaire notamment pour 2x bits |
Country Status (1)
| Country | Link |
|---|---|
| FR (1) | FR2296966A1 (enExample) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4176287A (en) * | 1978-04-13 | 1979-11-27 | Motorola, Inc. | Versatile CMOS decoder |
| EP0048820A3 (en) * | 1980-09-25 | 1983-09-07 | Deutsche Itt Industries Gmbh | Binary mos parallel comparators |
| EP0238677A1 (de) * | 1986-03-22 | 1987-09-30 | Deutsche ITT Industries GmbH | Schaltungsanordnung zur Koinzidenzüberprüfung eines Datenworts mit einem Referenzdatenwort |
-
1974
- 1974-12-31 FR FR7443621A patent/FR2296966A1/fr active Granted
Non-Patent Citations (3)
| Title |
|---|
| (PUBLICATION US "I.B.M. TECHNICAL DISCLOSURE BULLETIN", VOLUME 16, NO. 3, AOUT 1973, PAGE 1007, ARTICLE: "TWO-WAY EXCLUSIVE "OR" USING COMPLEMENTARY FETS" BENNETT ) * |
| *REVUE US "ELECTRONIC DESIGN", VOLUME 17, NO. 6, 15 MARS 1969, PAGES 64 ET 65, ARTICLE: "READERS SUGGEST SIMPLER DIGITAL COMPARATORS" FISHMAN ET HORELICK ) * |
| REVUE US "ELECTRONIC DESIGN", VOLUME 16, NO. 23, 7 NOVEMBRE 1968, PAGES 52 A 57, ARTICLE : "DESIGN DIGITAL COMPARATORS LOGICALLY" FRIM ET MILLER * |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4176287A (en) * | 1978-04-13 | 1979-11-27 | Motorola, Inc. | Versatile CMOS decoder |
| EP0048820A3 (en) * | 1980-09-25 | 1983-09-07 | Deutsche Itt Industries Gmbh | Binary mos parallel comparators |
| EP0238677A1 (de) * | 1986-03-22 | 1987-09-30 | Deutsche ITT Industries GmbH | Schaltungsanordnung zur Koinzidenzüberprüfung eines Datenworts mit einem Referenzdatenwort |
| US4812809A (en) * | 1986-03-22 | 1989-03-14 | Deutsche Itt Industries Gmbh | Circuit for checking the coincidence of a data word with a reference data word |
Also Published As
| Publication number | Publication date |
|---|---|
| FR2296966B1 (enExample) | 1977-07-08 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| ST | Notification of lapse |