FR2255656A1 - Data processing system with working storage - has instruction register, index registers, arithmetic unit, address register and control unit - Google Patents
Data processing system with working storage - has instruction register, index registers, arithmetic unit, address register and control unitInfo
- Publication number
- FR2255656A1 FR2255656A1 FR7442313A FR7442313A FR2255656A1 FR 2255656 A1 FR2255656 A1 FR 2255656A1 FR 7442313 A FR7442313 A FR 7442313A FR 7442313 A FR7442313 A FR 7442313A FR 2255656 A1 FR2255656 A1 FR 2255656A1
- Authority
- FR
- France
- Prior art keywords
- register
- address
- working storage
- data processing
- processing system
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
- G06F9/355—Indexed addressing
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Executing Machine-Instructions (AREA)
- Complex Calculations (AREA)
Abstract
The apparatus is used with memory matrices and a further storage word is addressed in the working storage in dependence on a chain bit set in the instruction word register. It is addressed by an incremental increase of the instruction counter and entered in the instruction word register. The contents of the index register given in the storage word is used in the known indexing of the address still stored in the address register from the previous address generation. The end of the address generation with the following addressing of of a data word in the working storage with the address stored in the address register is determined by the erased chain bit.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19732365091 DE2365091A1 (en) | 1973-12-22 | 1973-12-22 | DATA PROCESSING SYSTEM WITH A WORKING MEMORY |
Publications (1)
Publication Number | Publication Date |
---|---|
FR2255656A1 true FR2255656A1 (en) | 1975-07-18 |
Family
ID=5902204
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR7442313A Withdrawn FR2255656A1 (en) | 1973-12-22 | 1974-12-20 | Data processing system with working storage - has instruction register, index registers, arithmetic unit, address register and control unit |
Country Status (2)
Country | Link |
---|---|
DE (1) | DE2365091A1 (en) |
FR (1) | FR2255656A1 (en) |
-
1973
- 1973-12-22 DE DE19732365091 patent/DE2365091A1/en active Pending
-
1974
- 1974-12-20 FR FR7442313A patent/FR2255656A1/en not_active Withdrawn
Also Published As
Publication number | Publication date |
---|---|
DE2365091A1 (en) | 1975-07-03 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |