GB1397718A - Analysis of data - Google Patents

Abstract

1397718 Error handling INTERNATIONAL BUSINESS MACHINES CORP 23 Aug 1973 [26 Sept 1972] 40007/73 Headings G4H and G4A Which bit positions are the same in each of a plurality of multi-bit words is determined by ORing each word in turn into (i.e. with its current contents) a first register (preset to all zeroes) and ANDing each word in turn into a second register (preset to all ones), then EXCLORing corresponding positions of the two registers. If a given bit position is not the same in all the words then it will be 0 at least once and 1 at least once so the ORing will give 1 and the ANDing will give 0, and so the EXCL-ORing will give 1. Otherwise the EXCL-ORing will give 0. It is stated that whether the error involves a 0 substituted for a 1 or vice versa can be determined from the final contents of the two registers. Each word may be the concatenation of the outputs of an arithmetic-and-logic-unit, two operand registers feeding it, a result register fed from it and a parity error bit, and may be stored in an error store on detection of a parity error at the output of the result register, the error store feeding the ORing and ANDing &c. arrangements above. The two registers in the latter may be addressable locations in the error store.