FR2115162A1 - - Google Patents
Info
- Publication number
- FR2115162A1 FR2115162A1 FR7137572A FR7137572A FR2115162A1 FR 2115162 A1 FR2115162 A1 FR 2115162A1 FR 7137572 A FR7137572 A FR 7137572A FR 7137572 A FR7137572 A FR 7137572A FR 2115162 A1 FR2115162 A1 FR 2115162A1
- Authority
- FR
- France
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/10—DRAM devices comprising bipolar components
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/4067—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the bipolar type
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4094—Bit-line management or control circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
- H10D84/611—Combinations of BJTs and one or more of diodes, resistors or capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Static Random-Access Memory (AREA)
- Semiconductor Memories (AREA)
- Dram (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US9296170A | 1970-11-27 | 1970-11-27 | |
| US9296070A | 1970-11-27 | 1970-11-27 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| FR2115162A1 true FR2115162A1 (instruction) | 1972-07-07 |
| FR2115162B1 FR2115162B1 (instruction) | 1974-05-31 |
Family
ID=26786240
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| FR7137573A Expired FR2115163B1 (instruction) | 1970-11-27 | 1971-10-12 | |
| FR7137572A Expired FR2115162B1 (instruction) | 1970-11-27 | 1971-10-12 |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| FR7137573A Expired FR2115163B1 (instruction) | 1970-11-27 | 1971-10-12 |
Country Status (8)
| Country | Link |
|---|---|
| US (2) | US3729719A (instruction) |
| AU (1) | AU451906B2 (instruction) |
| CA (2) | CA948328A (instruction) |
| CH (1) | CH531772A (instruction) |
| DE (1) | DE2156805C3 (instruction) |
| FR (2) | FR2115163B1 (instruction) |
| GB (1) | GB1336482A (instruction) |
| NL (1) | NL179425C (instruction) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2204849A1 (instruction) * | 1972-11-01 | 1974-05-24 | Ibm |
Families Citing this family (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3919569A (en) * | 1972-12-29 | 1975-11-11 | Ibm | Dynamic two device memory cell which provides D.C. sense signals |
| JPS5017180A (instruction) * | 1973-06-13 | 1975-02-22 | ||
| US3893146A (en) * | 1973-12-26 | 1975-07-01 | Teletype Corp | Semiconductor capacitor structure and memory cell, and method of making |
| US3918033A (en) * | 1974-11-11 | 1975-11-04 | Ibm | SCR memory cell |
| US4084174A (en) * | 1976-02-12 | 1978-04-11 | Fairchild Camera And Instrument Corporation | Graduated multiple collector structure for inverted vertical bipolar transistors |
| US4090254A (en) * | 1976-03-01 | 1978-05-16 | International Business Machines Corporation | Charge injector transistor memory |
| FR2365858A1 (fr) * | 1976-09-24 | 1978-04-21 | Thomson Csf | Memoire non volatile de longue duree pour signaux rapides |
| FR2365859A1 (fr) * | 1976-09-24 | 1978-04-21 | Thomson Csf | Memoire non volatile pour signaux rapides |
| US4125855A (en) * | 1977-03-28 | 1978-11-14 | Bell Telephone Laboratories, Incorporated | Integrated semiconductor crosspoint arrangement |
| US4181981A (en) * | 1977-12-30 | 1980-01-01 | International Business Machines Corporation | Bipolar two device dynamic memory cell |
| JPS55145363A (en) * | 1979-04-27 | 1980-11-12 | Toshiba Corp | Semiconductor device |
| US4476623A (en) * | 1979-10-22 | 1984-10-16 | International Business Machines Corporation | Method of fabricating a bipolar dynamic memory cell |
| US4309716A (en) * | 1979-10-22 | 1982-01-05 | International Business Machines Corporation | Bipolar dynamic memory cell |
| US4409673A (en) * | 1980-12-31 | 1983-10-11 | Ibm Corporation | Single isolation cell for DC stable memory |
| US4882706A (en) * | 1985-06-07 | 1989-11-21 | Anamartic Limited | Data storage element and memory structures employing same |
| TW223172B (en) * | 1992-12-22 | 1994-05-01 | Siemens Ag | Siganl sensing circuits for memory system using dynamic gain memory cells |
| US5793668A (en) * | 1997-06-06 | 1998-08-11 | Timeplex, Inc. | Method and apparatus for using parasitic capacitances of a printed circuit board as a temporary data storage medium working with a remote device |
| US6128216A (en) * | 1998-05-13 | 2000-10-03 | Micron Technology Inc. | High density planar SRAM cell with merged transistors |
| US7376008B2 (en) * | 2003-08-07 | 2008-05-20 | Contour Seminconductor, Inc. | SCR matrix storage device |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB771625A (en) * | 1953-12-31 | 1957-04-03 | Ibm | Electric charge storage apparatus |
| NL294168A (instruction) * | 1963-06-17 | |||
| US3388292A (en) * | 1966-02-15 | 1968-06-11 | Rca Corp | Insulated gate field-effect transistor means for information gating and driving of solid state display panels |
| US3475735A (en) * | 1967-05-09 | 1969-10-28 | Honeywell Inc | Semiconductor memory |
| US3518635A (en) * | 1967-08-22 | 1970-06-30 | Bunker Ramo | Digital memory apparatus |
| US3513365A (en) * | 1968-06-24 | 1970-05-19 | Mark W Levi | Field-effect integrated circuit and method of fabrication |
| US3599180A (en) * | 1968-11-29 | 1971-08-10 | Gen Instrument Corp | Random access read-write memory system having data refreshing capabilities and memory cell therefor |
| US3576571A (en) * | 1969-01-07 | 1971-04-27 | North American Rockwell | Memory circuit using storage capacitance and field effect devices |
| US3581292A (en) * | 1969-01-07 | 1971-05-25 | North American Rockwell | Read/write memory circuit |
| US3582909A (en) * | 1969-03-07 | 1971-06-01 | North American Rockwell | Ratioless memory circuit using conditionally switched capacitor |
| US3593037A (en) * | 1970-03-13 | 1971-07-13 | Intel Corp | Cell for mos random-acess integrated circuit memory |
-
1970
- 1970-11-27 US US00092960A patent/US3729719A/en not_active Expired - Lifetime
- 1970-11-27 US US92961A patent/US3697962A/en not_active Expired - Lifetime
-
1971
- 1971-10-12 FR FR7137573A patent/FR2115163B1/fr not_active Expired
- 1971-10-12 FR FR7137572A patent/FR2115162B1/fr not_active Expired
- 1971-10-29 AU AU35152/71A patent/AU451906B2/en not_active Expired
- 1971-11-12 CA CA127,429A patent/CA948328A/en not_active Expired
- 1971-11-12 CA CA127,432A patent/CA954220A/en not_active Expired
- 1971-11-12 CH CH1649771A patent/CH531772A/de not_active IP Right Cessation
- 1971-11-16 DE DE2156805A patent/DE2156805C3/de not_active Expired
- 1971-11-17 GB GB5341371A patent/GB1336482A/en not_active Expired
- 1971-11-25 NL NLAANVRAGE7116191,A patent/NL179425C/xx not_active IP Right Cessation
Non-Patent Citations (1)
| Title |
|---|
| REVUE AMERICAINE "IBM TECHNICAL DISCLOSURE BELLETIN", VOLUME 13, NO.1, JUIN 1970, PAGES 84-85:"MEMORY WITH COMBINED READ-WRITE OPERATION" D.TAYLOR * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2204849A1 (instruction) * | 1972-11-01 | 1974-05-24 | Ibm |
Also Published As
| Publication number | Publication date |
|---|---|
| FR2115163A1 (instruction) | 1972-07-07 |
| FR2115163B1 (instruction) | 1974-05-31 |
| GB1336482A (en) | 1973-11-07 |
| NL179425B (nl) | 1986-04-01 |
| DE2156805A1 (de) | 1972-06-22 |
| US3729719A (en) | 1973-04-24 |
| DE2156805B2 (de) | 1976-10-21 |
| AU451906B2 (en) | 1974-08-22 |
| FR2115162B1 (instruction) | 1974-05-31 |
| DE2155228A1 (de) | 1972-06-08 |
| CA954220A (en) | 1974-09-03 |
| DE2155228B2 (de) | 1976-10-14 |
| US3697962A (en) | 1972-10-10 |
| CH531772A (de) | 1972-12-15 |
| CA948328A (en) | 1974-05-28 |
| NL179425C (nl) | 1986-09-01 |
| AU3515271A (en) | 1973-05-03 |
| NL7116191A (instruction) | 1972-05-30 |
| DE2156805C3 (de) | 1985-02-07 |
Similar Documents
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| ST | Notification of lapse |