FR2071924A1 - Mémoire à plusieurs positions accessibles simultanément - Google Patents

Mémoire à plusieurs positions accessibles simultanément

Info

Publication number
FR2071924A1
FR2071924A1 FR7036830A FR7036830A FR2071924A1 FR 2071924 A1 FR2071924 A1 FR 2071924A1 FR 7036830 A FR7036830 A FR 7036830A FR 7036830 A FR7036830 A FR 7036830A FR 2071924 A1 FR2071924 A1 FR 2071924A1
Authority
FR
France
Prior art keywords
memory
several positions
accessible simultaneously
positions accessible
several
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7036830A
Other languages
English (en)
French (fr)
Other versions
FR2071924B1 (enExample
Inventor
Eugene Kolankowsky
Mahon Robert F Mc
David J Perlman
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of FR2071924A1 publication Critical patent/FR2071924A1/fr
Application granted granted Critical
Publication of FR2071924B1 publication Critical patent/FR2071924B1/fr
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
FR7036830A 1969-12-19 1970-10-06 Mémoire à plusieurs positions accessibles simultanément Granted FR2071924A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US88651169A 1969-12-19 1969-12-19
US88650969A 1969-12-19 1969-12-19

Publications (2)

Publication Number Publication Date
FR2071924A1 true FR2071924A1 (fr) 1971-09-24
FR2071924B1 FR2071924B1 (enExample) 1973-11-23

Family

ID=27128800

Family Applications (2)

Application Number Title Priority Date Filing Date
FR7036831A Expired FR2073480B1 (enExample) 1969-12-19 1970-10-06
FR7036830A Granted FR2071924A1 (fr) 1969-12-19 1970-10-06 Mémoire à plusieurs positions accessibles simultanément

Family Applications Before (1)

Application Number Title Priority Date Filing Date
FR7036831A Expired FR2073480B1 (enExample) 1969-12-19 1970-10-06

Country Status (4)

Country Link
US (2) US3643236A (enExample)
DE (2) DE2038483A1 (enExample)
FR (2) FR2073480B1 (enExample)
GB (2) GB1323733A (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2533738A1 (fr) * 1982-09-24 1984-03-30 Hitachi Ltd Dispositif de memoire a semiconducteurs
WO2009022024A1 (es) * 2007-08-02 2009-02-19 Jose Daniel Llopis Llopis Sistema electrónico de emulación de la cadena de la estructura de 'adn' de un cromosoma

Families Citing this family (37)

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JPS4942249A (enExample) * 1972-03-06 1974-04-20
JPS5618964B2 (enExample) * 1972-03-06 1981-05-02
JPS49108932A (enExample) * 1973-02-19 1974-10-16
JPS5433816B2 (enExample) * 1974-01-28 1979-10-23
SU576608A1 (ru) * 1975-02-13 1977-10-15 Предприятие П/Я М-5769 Ассоциативное запоминающее устройство
DE2517565C3 (de) * 1975-04-21 1978-10-26 Siemens Ag, 1000 Berlin Und 8000 Muenchen Schaltungsanordnung für ein Datenverarbeitungssystem
US4104719A (en) * 1976-05-20 1978-08-01 The United States Of America As Represented By The Secretary Of The Navy Multi-access memory module for data processing systems
US4053873A (en) * 1976-06-30 1977-10-11 International Business Machines Corporation Self-isolating cross-coupled sense amplifier latch circuit
SU624295A1 (ru) * 1976-08-17 1978-09-15 Предприятие П/Я В-2892 Ячейка пам ти дл матричной однородной структуры
US4120048A (en) * 1977-12-27 1978-10-10 Rockwell International Corporation Memory with simultaneous sequential and random address modes
EP0011375A1 (en) * 1978-11-17 1980-05-28 Motorola, Inc. Multi-port ram structure for data processor registers
US4193127A (en) * 1979-01-02 1980-03-11 International Business Machines Corporation Simultaneous read/write cell
JPS5634179A (en) * 1979-08-24 1981-04-06 Mitsubishi Electric Corp Control circuit for memory unit
US4280197A (en) * 1979-12-07 1981-07-21 Ibm Corporation Multiple access store
JPS56140390A (en) * 1980-04-04 1981-11-02 Nippon Electric Co Picture memory
DE3313441A1 (de) * 1983-04-13 1984-10-18 Siemens AG, 1000 Berlin und 8000 München Halbleiterspeicher
GB2164767B (en) * 1984-09-25 1988-08-24 Sony Corp Video data storage
GB2165066B (en) * 1984-09-25 1988-08-24 Sony Corp Video data storage
US4744078A (en) * 1985-05-13 1988-05-10 Gould Inc. Multiple path multiplexed host to network data communication system
US5165039A (en) * 1986-03-28 1992-11-17 Texas Instruments Incorporated Register file for bit slice processor with simultaneous accessing of plural memory array cells
EP0257987B1 (en) * 1986-08-22 1991-11-06 Fujitsu Limited Semiconductor memory device
US4845669A (en) * 1988-04-27 1989-07-04 International Business Machines Corporation Transporsable memory architecture
EP0390907B1 (en) * 1988-10-07 1996-07-03 Martin Marietta Corporation Parallel data processor
KR920009059B1 (ko) * 1989-12-29 1992-10-13 삼성전자 주식회사 반도체 메모리 장치의 병렬 테스트 방법
US5235543A (en) * 1989-12-29 1993-08-10 Intel Corporation Dual port static memory with one cycle read-modify-write
US5121360A (en) * 1990-06-19 1992-06-09 International Business Machines Corporation Video random access memory serial port access
US6073185A (en) * 1993-08-27 2000-06-06 Teranex, Inc. Parallel data processor
US6173388B1 (en) 1998-04-09 2001-01-09 Teranex Inc. Directly accessing local memories of array processors for improved real-time corner turning processing
US6067609A (en) * 1998-04-09 2000-05-23 Teranex, Inc. Pattern generation and shift plane operations for a mesh connected computer
US6212628B1 (en) 1998-04-09 2001-04-03 Teranex, Inc. Mesh connected computer
US6185667B1 (en) 1998-04-09 2001-02-06 Teranex, Inc. Input/output support for processing in a mesh connected computer
US6587917B2 (en) * 2001-05-29 2003-07-01 Agilent Technologies, Inc. Memory architecture for supporting concurrent access of different types
US6944739B2 (en) * 2001-09-20 2005-09-13 Microchip Technology Incorporated Register bank
US6765834B2 (en) * 2002-11-19 2004-07-20 Hewlett-Packard Development Company, L.P. System and method for sensing memory cells of an array of memory cells
US8351236B2 (en) 2009-04-08 2013-01-08 Sandisk 3D Llc Three-dimensional array of re-programmable non-volatile memory elements having vertical bit lines and a single-sided word line architecture
US20110297912A1 (en) 2010-06-08 2011-12-08 George Samachisa Non-Volatile Memory Having 3d Array of Read/Write Elements with Vertical Bit Lines and Laterally Aligned Active Elements and Methods Thereof
US8526237B2 (en) 2010-06-08 2013-09-03 Sandisk 3D Llc Non-volatile memory having 3D array of read/write elements and read/write circuits and method thereof

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2813260A (en) * 1954-10-29 1957-11-12 Rca Corp Magnetic device
US3292008A (en) * 1963-12-03 1966-12-13 Rca Corp Switching circuit having low standby power dissipation
US3363115A (en) * 1965-03-29 1968-01-09 Gen Micro Electronics Inc Integral counting circuit with storage capacitors in the conductive path of steering gate circuits
US3548388A (en) * 1968-12-05 1970-12-15 Ibm Storage cell with a charge transfer load including series connected fets

Non-Patent Citations (6)

* Cited by examiner, † Cited by third party
Title
(REVU AMERICAINE IFEE JOURNAL OF SOLID STATE CIRCUITS VOL.SC-3,NO.3,SEPTEMBRE 1968,ARTICLE:"A COINCIDENT SELECT MOS STORAGE ARRAY"PAR FRIEDRICH,PAGES 280-285 *
COINCIDENT SELECT MOS STORAGE ARRAY"PAR FRIEDRICH,PAGES 280-285 *
DIMENSIONAL DRIVE"PAR FUGERE ET RHODES,PAGES 55-56) *
REVUE AMERICAINE IBM TECHNICAL DISCLOSURE BULLETIN,VOL.4,NO.11,AVRIL 1962,ARTICLE:"MULTI- *
REVUE AMERICAINE IBM TECHNICAL DISCLOSURE BULLETIN,VOL.4,NO.11,AVRIL 1962,ARTICLE:"MULTI- DIMENSIONAL DRIVE"PAR FUGERE ET RHODES,PAGES 55-56) *
REVUE AMERICAINE IFEE JOURNAL OF SOLID STATE CIRCUITS VOL.SC-3,NO.3,SEPTEMBRE 1968,ARTICLE:"A *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2533738A1 (fr) * 1982-09-24 1984-03-30 Hitachi Ltd Dispositif de memoire a semiconducteurs
WO2009022024A1 (es) * 2007-08-02 2009-02-19 Jose Daniel Llopis Llopis Sistema electrónico de emulación de la cadena de la estructura de 'adn' de un cromosoma

Also Published As

Publication number Publication date
FR2073480B1 (enExample) 1973-11-23
US3638204A (en) 1972-01-25
DE2062211A1 (de) 1971-06-24
FR2073480A1 (enExample) 1971-10-01
US3643236A (en) 1972-02-15
DE2038483A1 (de) 1971-06-24
GB1316300A (en) 1973-05-09
FR2071924B1 (enExample) 1973-11-23
GB1323733A (en) 1973-07-18

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Legal Events

Date Code Title Description
ST Notification of lapse