FR2064138A1 - Semiconductor devices by etching - Google Patents
Semiconductor devices by etchingInfo
- Publication number
- FR2064138A1 FR2064138A1 FR7035132A FR7035132A FR2064138A1 FR 2064138 A1 FR2064138 A1 FR 2064138A1 FR 7035132 A FR7035132 A FR 7035132A FR 7035132 A FR7035132 A FR 7035132A FR 2064138 A1 FR2064138 A1 FR 2064138A1
- Authority
- FR
- France
- Prior art keywords
- etching
- lower layer
- semiconductor devices
- etching operation
- chemical solvent
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000005530 etching Methods 0.000 title abstract 5
- 239000004065 semiconductor Substances 0.000 title abstract 2
- 239000000463 material Substances 0.000 abstract 5
- 239000002904 solvent Substances 0.000 abstract 2
- 239000000126 substance Substances 0.000 abstract 2
- 229910052581 Si3N4 Inorganic materials 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
- H01L23/4855—Overhang structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Bipolar Transistors (AREA)
- Weting (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
IT5358869 | 1969-10-04 |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2064138A1 true FR2064138A1 (en) | 1971-07-16 |
FR2064138B1 FR2064138B1 (fr) | 1974-06-21 |
Family
ID=11283893
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR7035132A Granted FR2064138A1 (en) | 1969-10-04 | 1970-09-29 | Semiconductor devices by etching |
Country Status (5)
Country | Link |
---|---|
BE (1) | BE756729A (fr) |
DE (1) | DE2046872A1 (fr) |
FR (1) | FR2064138A1 (fr) |
IL (1) | IL35376A0 (fr) |
NL (1) | NL7014087A (fr) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2423846A1 (de) | 1973-05-16 | 1974-11-28 | Fujitsu Ltd | Verfahren zur herstellung eines halbleiter-bauelements |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2824026A1 (de) * | 1978-06-01 | 1979-12-20 | Licentia Gmbh | Verfahren zum herstellen eines sperrschicht-feldeffekttransistors |
US4544443A (en) * | 1983-05-13 | 1985-10-01 | Shap Kabushiki Kaisha | Method for manufacturing an optical memory element |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR1570896A (fr) * | 1967-06-22 | 1969-06-13 |
-
0
- BE BE756729D patent/BE756729A/fr unknown
-
1970
- 1970-09-23 DE DE19702046872 patent/DE2046872A1/de active Pending
- 1970-09-24 NL NL7014087A patent/NL7014087A/xx unknown
- 1970-09-29 FR FR7035132A patent/FR2064138A1/fr active Granted
- 1970-09-30 IL IL35376A patent/IL35376A0/xx unknown
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR1570896A (fr) * | 1967-06-22 | 1969-06-13 |
Non-Patent Citations (8)
Title |
---|
(REVUE NEERLENDAISE PHILIPS RESEARCH REPORTS,VOL.25,AVRIL 1970"LOCAL OXIDATION OF SILICON AND ITS APPLICATION IN SEMICONDUCTEUR DEVICE TECHNOLOGY",J.A.APPELS ET AL,PAGES 118-132,CONFERENCE:EXETER GRANDE-BRETAGNE ,SEPTEMBRE 1969. * |
872.) * |
EXETER GRANDE-BRETAGNE ,SEPTEMBRE 1969. * |
ITS APPLICATION IN SEMICONDUCTEUR DEVICE TECHNOLOGY",J.A.APPELS ET AL,PAGES 118-132,CONFERENCE: * |
REVUE AMERICAINE JOURNAL OF THE ELECTROCHEMICAL SOCIETY,VOL.114,AOUT 1967,"THE ETCHING OF * |
REVUE AMERICAINE JOURNAL OF THE ELECTROCHEMICAL SOCIETY,VOL.114,AOUT 1967,"THE ETCHING OF SILICON NITRIDE IN PHOSPHORIC ACID WITH SILICON DIOXIDE AS A MASK"W.VAN GELDER ET AL,PAGES 869-872.) * |
REVUE NEERLENDAISE PHILIPS RESEARCH REPORTS,VOL.25,AVRIL 1970"LOCAL OXIDATION OF SILICON AND * |
SILICON NITRIDE IN PHOSPHORIC ACID WITH SILICON DIOXIDE AS A MASK"W.VAN GELDER ET AL,PAGES 869- * |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2423846A1 (de) | 1973-05-16 | 1974-11-28 | Fujitsu Ltd | Verfahren zur herstellung eines halbleiter-bauelements |
DE2462644C2 (de) * | 1973-05-16 | 1982-03-04 | Fujitsu Ltd., Kawasaki, Kanagawa | Verfahren zur Herstellung eines Transistors |
Also Published As
Publication number | Publication date |
---|---|
DE2046872A1 (de) | 1971-05-19 |
BE756729A (fr) | 1971-03-01 |
NL7014087A (fr) | 1971-04-06 |
IL35376A0 (en) | 1970-11-30 |
FR2064138B1 (fr) | 1974-06-21 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |