IL35376A0 - Method for the production of semiconductor devices - Google Patents

Method for the production of semiconductor devices

Info

Publication number
IL35376A0
IL35376A0 IL35376A IL3537670A IL35376A0 IL 35376 A0 IL35376 A0 IL 35376A0 IL 35376 A IL35376 A IL 35376A IL 3537670 A IL3537670 A IL 3537670A IL 35376 A0 IL35376 A0 IL 35376A0
Authority
IL
Israel
Prior art keywords
production
semiconductor devices
semiconductor
devices
Prior art date
Application number
IL35376A
Original Assignee
Semiconduttori Spa Sgs Soc Gen
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconduttori Spa Sgs Soc Gen filed Critical Semiconduttori Spa Sgs Soc Gen
Publication of IL35376A0 publication Critical patent/IL35376A0/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H01L23/4855Overhang structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/311Etching the insulating layers by chemical or physical means
    • H01L21/31105Etching inorganic layers
    • H01L21/31111Etching inorganic layers by chemical means
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Bipolar Transistors (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Weting (AREA)
IL35376A 1969-10-04 1970-09-30 Method for the production of semiconductor devices IL35376A0 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT5358869 1969-10-04

Publications (1)

Publication Number Publication Date
IL35376A0 true IL35376A0 (en) 1970-11-30

Family

ID=11283893

Family Applications (1)

Application Number Title Priority Date Filing Date
IL35376A IL35376A0 (en) 1969-10-04 1970-09-30 Method for the production of semiconductor devices

Country Status (5)

Country Link
BE (1) BE756729A (en)
DE (1) DE2046872A1 (en)
FR (1) FR2064138A1 (en)
IL (1) IL35376A0 (en)
NL (1) NL7014087A (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3940288A (en) * 1973-05-16 1976-02-24 Fujitsu Limited Method of making a semiconductor device
DE2824026A1 (en) * 1978-06-01 1979-12-20 Licentia Gmbh Barrier layer FET - mfd. by under etching bottom mask layer to cover barrier layer surface
US4544443A (en) * 1983-05-13 1985-10-01 Shap Kabushiki Kaisha Method for manufacturing an optical memory element

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1614829C3 (en) * 1967-06-22 1974-04-04 Telefunken Patentverwertungs Gmbh, 7900 Ulm Method for manufacturing a semiconductor component

Also Published As

Publication number Publication date
NL7014087A (en) 1971-04-06
FR2064138A1 (en) 1971-07-16
DE2046872A1 (en) 1971-05-19
BE756729A (en) 1971-03-01
FR2064138B1 (en) 1974-06-21

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