FI982374A0 - Minnesgränssnitt - Google Patents
MinnesgränssnittInfo
- Publication number
- FI982374A0 FI982374A0 FI982374A FI982374A FI982374A0 FI 982374 A0 FI982374 A0 FI 982374A0 FI 982374 A FI982374 A FI 982374A FI 982374 A FI982374 A FI 982374A FI 982374 A0 FI982374 A0 FI 982374A0
- Authority
- FI
- Finland
- Prior art keywords
- memory interface
- interface
- memory
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
- G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
- Communication Control (AREA)
- Memory System (AREA)
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FI982374A FI982374A (sv) | 1998-11-02 | 1998-11-02 | Minnesgränssnitt |
| EP99660166A EP1001350A3 (en) | 1998-11-02 | 1999-10-27 | Memory interface |
| US09/430,899 US6598116B1 (en) | 1998-11-02 | 1999-11-01 | Memory interface using only one address strobe line |
| KR1019990048179A KR20000035167A (ko) | 1998-11-02 | 1999-11-02 | 메모리, 메모리 어드레스 전송 방법 및 메모리 인터페이스 |
| JP11312557A JP2000181854A (ja) | 1998-11-02 | 1999-11-02 | メモリへアドレスを伝送する方法およびメモリ |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| FI982374A FI982374A (sv) | 1998-11-02 | 1998-11-02 | Minnesgränssnitt |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| FI982374A0 true FI982374A0 (sv) | 1998-11-02 |
| FI982374A FI982374A (sv) | 2000-06-21 |
Family
ID=8552831
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| FI982374A FI982374A (sv) | 1998-11-02 | 1998-11-02 | Minnesgränssnitt |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US6598116B1 (sv) |
| EP (1) | EP1001350A3 (sv) |
| JP (1) | JP2000181854A (sv) |
| KR (1) | KR20000035167A (sv) |
| FI (1) | FI982374A (sv) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6112287A (en) * | 1993-03-01 | 2000-08-29 | Busless Computers Sarl | Shared memory multiprocessor system using a set of serial links as processors-memory switch |
| US6728150B2 (en) * | 2002-02-11 | 2004-04-27 | Micron Technology, Inc. | Method and apparatus for supplementary command bus |
| US7376092B2 (en) * | 2002-04-03 | 2008-05-20 | Precache Inc. | Method and apparatus for implementing persistent and reliable message delivery |
| US7177230B1 (en) * | 2005-08-25 | 2007-02-13 | Mediatek Inc. | Memory controller and memory system |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE2948159C2 (de) | 1979-11-29 | 1983-10-27 | Siemens AG, 1000 Berlin und 8000 München | Integrierter Speicherbaustein mit wählbaren Betriebsfunktionen |
| US5179687A (en) * | 1987-09-26 | 1993-01-12 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device containing a cache and an operation method thereof |
| US4939692A (en) * | 1988-09-15 | 1990-07-03 | Intel Corporation | Read-only memory for microprocessor systems having shared address/data lines |
| JPH02177190A (ja) * | 1988-12-28 | 1990-07-10 | Nec Corp | メモリ装置 |
| JP2777247B2 (ja) * | 1990-01-16 | 1998-07-16 | 三菱電機株式会社 | 半導体記憶装置およびキャッシュシステム |
| US5249160A (en) * | 1991-09-05 | 1993-09-28 | Mosel | SRAM with an address and data multiplexer |
| US5430676A (en) * | 1993-06-02 | 1995-07-04 | Rambus, Inc. | Dynamic random access memory system |
| US5634105A (en) * | 1994-07-21 | 1997-05-27 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device to interface control signals for a DRAM to a SRAM |
| US5537353A (en) * | 1995-08-31 | 1996-07-16 | Cirrus Logic, Inc. | Low pin count-wide memory devices and systems and methods using the same |
| US6215497B1 (en) * | 1998-08-12 | 2001-04-10 | Monolithic System Technology, Inc. | Method and apparatus for maximizing the random access bandwidth of a multi-bank DRAM in a computer graphics system |
| US6130843A (en) * | 1998-09-02 | 2000-10-10 | Micron Technology, Inc. | Method and circuit for providing a memory device having hidden row access and row precharge times |
-
1998
- 1998-11-02 FI FI982374A patent/FI982374A/sv unknown
-
1999
- 1999-10-27 EP EP99660166A patent/EP1001350A3/en not_active Withdrawn
- 1999-11-01 US US09/430,899 patent/US6598116B1/en not_active Expired - Fee Related
- 1999-11-02 JP JP11312557A patent/JP2000181854A/ja active Pending
- 1999-11-02 KR KR1019990048179A patent/KR20000035167A/ko not_active Application Discontinuation
Also Published As
| Publication number | Publication date |
|---|---|
| JP2000181854A (ja) | 2000-06-30 |
| US6598116B1 (en) | 2003-07-22 |
| EP1001350A3 (en) | 2004-01-02 |
| EP1001350A2 (en) | 2000-05-17 |
| FI982374A (sv) | 2000-06-21 |
| KR20000035167A (ko) | 2000-06-26 |
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