FI925428A0 - FOERFARANDE OCH ANORDNING FOER SIGNALTEKNISKT SAEKER MATNING AV BINAERA SIGNALER TILL ETT SIGNALTEKNISKT SAEKERT DATORSYSTEM - Google Patents

FOERFARANDE OCH ANORDNING FOER SIGNALTEKNISKT SAEKER MATNING AV BINAERA SIGNALER TILL ETT SIGNALTEKNISKT SAEKERT DATORSYSTEM

Info

Publication number
FI925428A0
FI925428A0 FI925428A FI925428A FI925428A0 FI 925428 A0 FI925428 A0 FI 925428A0 FI 925428 A FI925428 A FI 925428A FI 925428 A FI925428 A FI 925428A FI 925428 A0 FI925428 A0 FI 925428A0
Authority
FI
Finland
Prior art keywords
signaltekniskt
saekert
saeker
datorsystem
binaera
Prior art date
Application number
FI925428A
Other languages
Finnish (fi)
Other versions
FI925428A (en
Inventor
Horst Strelow
Original Assignee
Siemens Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Ag filed Critical Siemens Ag
Publication of FI925428A0 publication Critical patent/FI925428A0/en
Publication of FI925428A publication Critical patent/FI925428A/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1629—Error detection by comparing the output of redundant processing systems
    • G06F11/1633—Error detection by comparing the output of redundant processing systems using mutual exchange of the output between the redundant processing components
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B61—RAILWAYS
    • B61L—GUIDING RAILWAY TRAFFIC; ENSURING THE SAFETY OF RAILWAY TRAFFIC
    • B61L1/00—Devices along the route controlled by interaction with the vehicle or train
    • B61L1/20—Safety arrangements for preventing or indicating malfunction of the device, e.g. by leakage current, by lightning
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0796—Safety measures, i.e. ensuring safe condition in the event of error, e.g. for controlling element
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1608—Error detection by comparing the output signals of redundant hardware
    • G06F11/1616—Error detection by comparing the output signals of redundant hardware where the redundant component is an I/O device or an adapter therefor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G06F11/2215—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test error correction or detection circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Automation & Control Theory (AREA)
  • Mechanical Engineering (AREA)
  • Input From Keyboards Or The Like (AREA)
  • Multi Processors (AREA)
  • Hardware Redundancy (AREA)

Abstract

The computers (MC1, MC2) of the computer system are associated with common input assemblies (S1.1) for the input signals (E1, E2) to be processed. These input signals are offered in two channels. The input signals corresponding to one another are ANDed with signal protection outside the computers and pass in this form to common input assemblies (S1.1). The input assemblies can be checked for correct operation in familiar manner. The individual computer which is supplied with the ANDed input signals transmits these to the remaining computers (MC2) of the computer system. When the method according to the invention is used, the amount of input assemblies in 2V2 systems which can be checked for their operability is reduced to 50%, and to 66% in the 2V3 system, of the amount compared with a computer system in which this method is not used. <IMAGE>
FI925428A 1991-12-13 1992-11-27 Foerfarande och anordning Foer signaltekniskt saeker matning av binaera signaler till ett signaltekniskt saekert datorsystem FI925428A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE4141731A DE4141731A1 (en) 1991-12-13 1991-12-13 METHOD AND DEVICE FOR SIGNAL-SAFE ENTRY OF BINARY SIGNALS IN A SIGNAL-SAFE COMPUTER SYSTEM

Publications (2)

Publication Number Publication Date
FI925428A0 true FI925428A0 (en) 1992-11-27
FI925428A FI925428A (en) 1993-06-14

Family

ID=6447332

Family Applications (1)

Application Number Title Priority Date Filing Date
FI925428A FI925428A (en) 1991-12-13 1992-11-27 Foerfarande och anordning Foer signaltekniskt saeker matning av binaera signaler till ett signaltekniskt saekert datorsystem

Country Status (5)

Country Link
EP (1) EP0546647B1 (en)
AT (1) ATE149707T1 (en)
DE (2) DE4141731A1 (en)
DK (1) DK0546647T3 (en)
FI (1) FI925428A (en)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3503287A1 (en) * 1985-01-31 1986-08-07 Siemens AG, 1000 Berlin und 8000 München Input/output circuit for microcomputers for detecting registers operating defectively

Also Published As

Publication number Publication date
FI925428A (en) 1993-06-14
EP0546647B1 (en) 1997-03-05
ATE149707T1 (en) 1997-03-15
EP0546647A3 (en) 1994-10-19
DE4141731A1 (en) 1993-06-17
EP0546647A2 (en) 1993-06-16
DE59208117D1 (en) 1997-04-10
DK0546647T3 (en) 1997-09-22

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Legal Events

Date Code Title Description
FD Application lapsed