SE8201874L - Hierarchical structured information processing system - Google Patents

Hierarchical structured information processing system

Info

Publication number
SE8201874L
SE8201874L SE8201874A SE8201874A SE8201874L SE 8201874 L SE8201874 L SE 8201874L SE 8201874 A SE8201874 A SE 8201874A SE 8201874 A SE8201874 A SE 8201874A SE 8201874 L SE8201874 L SE 8201874L
Authority
SE
Sweden
Prior art keywords
processing system
multiple errors
information processing
tolerated
planes
Prior art date
Application number
SE8201874A
Other languages
Unknown language ( )
Swedish (sv)
Inventor
J Nikolaizik
K Richter
H Henning
M Kickbusch
K Brunecke
Original Assignee
Werk Signal Sicherungstech Veb
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Werk Signal Sicherungstech Veb filed Critical Werk Signal Sicherungstech Veb
Publication of SE8201874L publication Critical patent/SE8201874L/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/18—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits
    • G06F11/183—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits by voting, the voting not being performed by the redundant components
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/18—Error detection or correction of the data by redundancy in hardware using passive fault-masking of the redundant circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Hardware Redundancy (AREA)
  • Multi Processors (AREA)
  • Image Processing (AREA)
  • Medicines Containing Antibodies Or Antigens For Use As Internal Diagnostic Agents (AREA)

Abstract

A circuit arrangement for process automation by means of a hierarchical data processing system can be used in fields where high reliability and security are required. Enhancement is effected of the reliability and security of a hierarchical data processing system wherein single and multiple errors in different 'm-from-n' computer structures in a level or plane and multiple errors in different levels or planes are tolerated. Multiple errors which are not tolerated can be detected. Data transmission between the individual levels or planes is included in the majority decision. Using modular 'm-from-n' decision means ensures universal application of the redundancy principle within the hierarchy. Each computer has an input/output unit (4) arranged at an input thereof, the unit (4) comprising first and second direction switching means (1,3) and an 'm-from-n' decision means (2). <IMAGE>
SE8201874A 1981-03-26 1982-03-24 Hierarchical structured information processing system SE8201874L (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DD81228620A DD160757A3 (en) 1981-03-26 1981-03-26 HIERARCHIC CONSTRUCTION INFORMATION PROCESSING SYSTEM

Publications (1)

Publication Number Publication Date
SE8201874L true SE8201874L (en) 1982-09-27

Family

ID=5529865

Family Applications (1)

Application Number Title Priority Date Filing Date
SE8201874A SE8201874L (en) 1981-03-26 1982-03-24 Hierarchical structured information processing system

Country Status (9)

Country Link
BG (1) BG41445A1 (en)
CS (1) CS264009B1 (en)
DD (1) DD160757A3 (en)
DE (1) DE3208131A1 (en)
FR (1) FR2502806A1 (en)
GB (1) GB2095877B (en)
HU (1) HU184533B (en)
IT (1) IT8248071A0 (en)
SE (1) SE8201874L (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4630211A (en) * 1984-04-23 1986-12-16 Pettis Charles D Watt-hour meter display for informing consumer of energy consumption

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2023117B2 (en) * 1970-05-05 1975-10-30 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Fail safe control for digital information - three channel supervisory control built into processing unit provides full transfer
US3783250A (en) * 1972-02-25 1974-01-01 Nasa Adaptive voting computer system

Also Published As

Publication number Publication date
DD160757A3 (en) 1984-02-29
CS172982A1 (en) 1985-08-15
GB2095877A (en) 1982-10-06
BG41445A1 (en) 1987-06-15
CS264009B1 (en) 1989-05-12
IT8248071A0 (en) 1982-03-24
GB2095877B (en) 1985-01-03
HU184533B (en) 1984-09-28
FR2502806A1 (en) 1982-10-01
DE3208131A1 (en) 1982-11-04

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