FI89758B - DIGITAL DQPSK-DECODARDELKRETS - Google Patents

Description

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Digital DQPSK decoder circuit

The invention relates to a digital DPQSK decoder circuit for recovering phase difference information from multi-bit phase information at the original data frequency of DPSK-5 data pairs.

In order to understand the invention, one must first start with the modulation method described in the art called Differential Quadrature Phase Shift Keying, from which the abbreviation DQPSK is derived. In this case, for synchronous transmission of serial binary data via a band-limited channel, the stream of binary data is initially grouped into a synchronized sequence of two consecutive data, i.e. two-bit-15 data, also called symbols, resulting in four digital words 00, 01, 10, 11. If binary data data frequency, then the symbol frequency is equal to half the data frequency.

These (two-bit) digital words can, when interpreted as coordinates of a rectangular coordinate system and when viewed as binary numbers in a • - two-complement representation, represent the intersection of a unit circle 4 with coordinate axes, i.e. four angles 0 ° 90 °, 180 ° and 270 °. In differential quadrature phase shift keying, such digital words are used as DPSK data pairs for each phase difference. . with respect to the phase value preceding the display so that, for example, the DPSK data pairs 00, 10, 11, respectively 01 correspond to phase differences 0 °, 90 ° or -270 °, ± 180 ° 3070 ° or -90 °, respectively.

For the transmission of a DPSK data pair, these are filtered analogously or digitally, in which case the frequency of the clock signal of both digital filters required for this purpose is generally higher than the above-mentioned clock frequency.

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In connection with the filtering, their output signals are subjected to quadrature amplitude modulation and, in the case of analogue filtering, suitably analog quadrature modulation, in contrast to digital filtering, suitably digital quadrature rimodulation is carried out, i.e. the carrier

After this quadrature modulation, the orthogonal signals of the two "channels" of the mo-10 are summed and then the digital analog is converted and transferred in this form to the transmission path.

On the receiver side, analog-to-digital conversion is initially performed at a correspondingly higher sampling rate with associated (digital) quadrature amplitude demodulation, so that both outputs have a stream of digital orthogonal signal pairs. Subsequent low-pass filtering of both channels yields a pair of signals from which the symbol frequency (= twice the data-20 frequency) must again be able to be reset in terms of frequency and phase. This can be done, for example, in "IEEE Transactions on Communications", May 1986, p. 423-429, as described.

Thus, also after the achieved signal shortening for the signal frequencies of both channels, these signals are passed to a phase discriminator, the output of which provides false information containing information about the phase difference that originally prevailed; however, these signals are still multi-bit digital words from which phase-difference data must be separated.

The invention according to the claims is applied to this, the task of which is to recover the phase difference data from the multi-location false data in the simplest and most elegant way possible, in addition to compensating for phase errors in the transmission path and the preceding 3 signal processing.

The invention will now be described in more detail with reference to the figure of the drawing, which shows a block diagram of one embodiment.

5 The phase information dd is derived for the first constant adder kl, to which the digital word "45 °" corresponding to the phase angle 45 ° is derived. Its output is at the first input of an adder sm, the output of which is connected to the sub-input of the first subtractor s1.

10 In addition, the circuit includes a second constant adder k2, for which a digital word "45 °" corresponding to a phase angle of 45 ° is also derived as standard and whose output must be subtracted at the input of the first subtractor sl from the output signal of the adder sm. to the second input, as well as to the input of the delay v and the second subtractor s2 must be subtracted to the input from the output of which said phase difference data dp can be taken, from which DPSK data pairs can be formed by simple decoding 20. The delay time of the delay v must be period time.

The output of the first subtractor sl is connected via a low-pass filter tp acting as a PLL loop filter to the second input of the adder sm.

By summing the 45 ° digital word into the false data dd and the sign location sb of the output signal of the adder sm as well as the highest value bit mb, a reliable recovery of the phase difference data is achieved. The 45 "summation provides, which is a particular advantage of the invention, that the decision areas of the respective angular values are in each case one of the four quarters of the coordinate system, which thus have coordinate axes within the respective boundaries.

The decoder circuit of the invention can be advantageously used in the presently used in England and Scandinavia.

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4 in the context of de-modulation of a stereo color television sound standard conceived as a method, the abbreviation of which appears to be "NICAM". Details of this standard are described, for example, in the "Specification of a Standard for UK Stereo with Television Transmissions" published by the IBA and the BBC in September 1986.

In this use, the output of the second subtractor s2 is followed by a DPSK decoder, which generates from the phase difference data the already mentioned Double-digit digital words, which are then passed to the "NICAM" decoder.

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Claims (2)

A digital DQPSK decoder circuit for recovering phase difference information (dp) from multi-bit false data (dd) at the original data frequency of DPSK data pairs, characterized by a first constant adder (kl) derived by a digital word corresponding to a phase angle of 45 ° ("45 ° ") and phase difference data (dd), 10 adder (sm) having a first input at the output of the first constant adder (kl), a first subtractor (sl) having a subtractor input connected to the output of adder (sm), a second subtractor (s2 ), from the output of which the -15 he difference data (dp) can be taken, the delay (v), the delay time of which is the same as the time of the data frequency period and the output of which is at the subtractor input of the second subtractor (s2), the second standard adder (k2) derived a digital word corresponding to 20 phase angles of 45 ° ("45 °"), whereby the input of the second subtractor (s2) is subtracted, the delay (v) and the second constant adder (k2) is fed by the sign bit (sb) and the most significant bit (mb) of the output signal of the adder (sm) and 25 low-pass filters (tp) as a PLL loop filter, through which the output of the first subtractor (sl) is connected to the second input of the adder (sm). Use of a decoder circuit according to claim 1 in a receiver circuit for a "NICAM" stereo color television audio standard. 6