KR0120592Y1 - Line discriminating circuit of image signal - Google Patents

Abstract

As the line discrimination circuit of the PAL system video discrimination line is discriminated by analog processing, the reliability of the discrimination is degraded and it is difficult to implement the integrated circuit. To this end, the carrier is removed from the PAL digital video signal to demodulate the two color difference signals BY and RY, and the processing line and the current processing line one line before each of the two color difference signals BY and RY demodulated during the burst period of the video signal. After detecting the sign for, the current line is discriminated from the signs of the previous line and the current line for each of the detected two color difference signals BY and RY. Therefore, as a digital processing circuit having a simple configuration, the line of the PAL system video signal can be accurately determined.

Description

Line discrimination circuit of video signal

1 is a circuit diagram of an embodiment of a line discrimination circuit according to the present invention.

2 is an operation timing diagram of each part of FIG.

* Explanation of symbols for main parts of the drawings

40: first accumulation circuit 42: second accumulation circuit

44: demodulation circuit 46: code detection circuit

48: discrimination circuit

The present invention relates to a circuit for discriminating lines of an image signal, and more particularly to a circuit for discriminating odd lines and even lines for a PAL (Phase Alternation by Line) video signal.

In general, PAL video signals have a phase difference between lines (scan lines) unlike NTSC (National Television System Committee) video signals. That is, when generating PAL video signal, the two color difference signals BY and RY are modulated by color carriers having a phase difference of 90 °. The phases of the color subcarriers modulating the color difference signal RY among the two color difference signals BY and RY are each line. Invert each other 180 °. Accordingly, even in the image processing apparatus which processes the PAL system signal, the PAL system video signal can be processed correctly only by determining whether the odd line or the even line is processed. If the processing line is erroneously discriminated, demodulation carriers are generated differently, which makes it impossible to demodulate or phase correct the distorted signal.

Accordingly, in the image processing apparatus for processing the PAL system video signal, it is essential to accurately determine the line for the PAL system video signal.

On the other hand, conventional line discrimination circuits have discriminated lines for PAL video signals using a circuit composed of analog elements. Accordingly, the circuit configuration is complicated and the reliability of the identification is not only lowered, but also difficult to implement as an integrated circuit, thereby increasing the volume of the circuit and increasing power consumption.

Accordingly, an object of the present invention is to provide a line discrimination circuit capable of accurately discriminating lines of a PAL video signal as a digital processing circuit having a simple configuration.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a circuit diagram of an embodiment of a line discrimination circuit according to the present invention,

A demodulation circuit 44 for demodulating two color difference signals B-Y and R-Y by removing a carrier from a PAL digital video signal VIDEO;

Code detection circuit 46 for detecting signals MSBBY, MSBPBY, MSBRY, and MSBPRY for the processing line one line before and the current processing line for each of the two color difference signals BY and RY demodulated during the burst period of the video signal. )Wow,

And a discrimination circuit 48 for discriminating the current line from the symbols MSBBY, MSBPBY, MSBRY, and MSBPRY of the previous line and the current line for each of the two color difference signals B-Y and R-Y detected by the code detection circuit 46.

In the structure of FIG. 1, the demodulation circuit 44 includes a multiplier 2 for multiplying the video signal VIDEO by a carrier wave fcu, and a first latch circuit for latching the color difference signal BY component B-Y 'among the output signals of the multiplier 2. 4) and a first low pass filter (Low) which extracts the color difference signal BY by removing the double carrier component by lowpass filtering the color difference signal BY component B-Y 'latched in the first latch circuit 4. 6), the second latch circuit 8 for latching the color difference signal RY component R-Y 'among the output signals of the multiplier 2, and the color difference latched in the second latch circuit 8; The second LPF 10 extracts the color difference signal RY by removing the double carrier component by lowpass filtering the signal RY component R-Y '.

The code detection circuit 46 latches the first accumulating circuit 40 which accumulates the color difference signal BY for each line during the burst period, and latches the most significant bit representing a sign in the sum SUMBY of the accumulated color difference signal BY, and thus, the first code bit MSBBY. The fifth latch circuit 16 outputting as a second latch bit and the first latch bit MSBBY latched in the fifth latch circuit 16 are latched every line, delayed for one line, and then outputted as the second code bit MSBPBY. The circuit 18, the second accumulating circuit 42 which accumulates the color difference signal RY for each burst period during the burst period, and the most significant bit representing the sign in the sum SUMRY of the accumulated color difference signal RY are latched as the third code bit MSBRY. An eighth latch circuit for latching the seventh latch circuit 24 for latching and the third code bit MSBRY latched in the seventh latch circuit 24 for each line, delaying for one line, and outputting the fourth code bit MSBPRY. It consists of 26. Here, the first accumulator circuit 40 adds the first adder 12 and the output of the first adder 12 to add the color difference signal BY outputted from the first LPF 6 to the sum SUMBY of the color difference signal BY of the previous pixels. A third latch circuit 14 is latched and applied to the first adder 12 and the fifth latch circuit 16 in common. The second accumulation circuit 42 latches the output of the second adder 20 and the second adder 20 that adds the color difference signal RY output from the second LPF 10 to the sum SUMRY of the color difference signal RY of the previous pixels. The fourth latch circuit 22 is applied to the second adder 20 and the seventh latch circuit 24.

The discrimination circuit 48 includes an exclusive OR gate 28 that performs an exclusive OR on the first and second code bits MSBBY and MSBPBY, and an exclusive NOR on the third and fourth code bits MSBRY and MSBPRY. An exclusive negative logic gate 30, an AND logic gate 32 that logically multiplies the outputs of the exclusive logical logic gate 28 and the exclusive negative logic gate 30, and an inverter for inverting the line discrimination signal PLINE for the previous line. 34, the exclusive logical sum gate 36 which exclusively ORs the outputs of the AND gate 32 and the inverter 34, and the outputs of the exclusive logical sum gate 36 are latched every line to determine a line discrimination signal for the current line. The ninth latch circuit 38 outputs as PLINE.

FIG. 2 shows the operation timing of each part of FIG.

Hereinafter, an operation example of FIG. 1 according to the present invention will be described in detail with reference to the operation timing diagram of FIG. 2.

First, the PAL system video signal VIDEO input to the line discrimination circuit of FIG. 1 is a digital signal, and two color difference signals B-Y and R-Y appear alternately as shown in FIG. The color difference signal of the video signal VIDEO is represented as shown in Table (1) along the line.

The video signal VIDEO as shown in Table 1 is multiplied by the demodulated carrier fcu in the multiplier 2. In this case, since the two color difference signals B-Y and R-Y appear alternately in the input video signal VIDEO as shown in FIG. 2, the demodulated carrier fcu varies according to the two color difference signals B-Y and R-Y as shown in Table 2 below.

In the PAL type image processing apparatus, a color carrier fsc is used as a modulation carrier when recording, and an fcu of 40fh is used as a demodulation carrier when playing back. Where fh is the horizontal scan frequency. When the result of the product of the input color signal and the demodulated carrier is only in the burst section, the color difference signal B-Y component B-Y 'and the color difference signal R-Y component R-Y' are as shown in Tables (3) and (4), respectively.

The color difference signal BY component B-Y 'as shown in Table 3 is latched to the first latch circuit 4 at the rising edge of the first clock signal CLK1, and the color difference signal RY as shown in Table 4 above. The component R-Y 'is latched to the second latch circuit 8 at the falling edge of the first clock signal CLK1, and then low-pass filtered by each of the first and second LPFs 6,10, thereby providing two. Double carrier component is removed. The first clock signal CLK1 is a sampling clock for the video signal VIDEO. The color difference signal BY output from the first LPF 6 is the same in both the odd and even lines, as shown in Equation (1) below, and the color difference signal RY output from the second LPF 10 is the following (2), ( 3)

The color difference signals B-Y and R-Y output from the first and second LPFs 6 and 10 are input to the first and second adders 12 and 20 of the code detection circuit 46, respectively.

In the present invention, the line discrimination for the PAL video signal is determined by using the codes of the color difference signals BY and RY of the odd and even lines output from the first and second LPFs 6 and 10. In 46), codes of the color difference signals BY and RY are detected.

If the nose line is correctly identified as the nose line, as shown in equations (1) and (2) above Becomes In addition, if it is determined that the storm line is the storm line, as shown in the above formulas (1) and (3) It becomes In this case, if the sign of the color difference signal BY and RY value is changed when θ changes with each set phase difference, the sign of the color difference signal BY and RY for the burst signal at the time of accurate line discrimination can be known as shown in the following table (5). Will be.

In the above table (5), it can be seen that the sign of the color difference signal B-Y is the same and the sign of the color difference signal R-Y is the opposite when the processing line before the current line and the current processing line are correctly identified. In other words, by comparing the codes of the color difference signals R-Y, it is possible to know whether the lines are correctly identified. However, it is impossible to determine the correct line if the phase error of the previous line and the phase error of the next line are two quadrants apart. For example, if the phase error θ of the preceding line is in the first quadrant (1θπ / 2) and the phase error of the back line is in the third quadrant (πθ3π / 2), then these two lines are Similarly, since the sign of the color difference signal RY is the same with the negative sign, it is determined that the line discrimination is wrong.

Therefore, correct line discrimination is possible only if the phase error between the two lines is within two quadrants.

On the other hand, when the line discrimination is incorrect, the color difference signals B-Y and R-Y of the burst section to be demodulated are as follows.

First, when the even line is identified as the odd line, the color difference signal B-Y component B-Y 'is expressed by the following expression (4).

At this time, the color difference signal B-Y output from the first LPF 6 is expressed by Equation 5 below.

The chrominance signal R-Y component R-Y 'is expressed by the following Equation (6).

At this time, the color difference signal R-Y output from the second LPF 10 is expressed by Equation 7 below.

Secondly, when the odd line is identified as the even line, the color difference signal B-Y component B-Y 'is expressed by the following expression (8).

At this time, the color difference signal B-Y output from the first LPF 6 is expressed by the following Equation (9).

The chrominance signal R-Y component R-Y 'is expressed by the following expression (10).

At this time, the color difference signal R-Y output from the second LPF 10 is expressed by Equation 11 below.

Using the equations (5), (7), (9), and (11) as described above, the signs of the color difference signals BY and RY when θ changes with a constant phase difference are examined as shown in Table (6). The color difference signal BY and RY codes for the burst signal in the case of the discrimination error can be known.

As can be seen from Table 6, when the line judgment is wrong, the signs of the color difference signals R-Y between the two lines are the same and the signs of the color difference signals B-Y are different. In other words, if the sign of the color difference signal B-Y is opposite between the two lines, it can be seen that the line discrimination at this time is wrong.

In this case, as in the case described above, the phase error between the two lines is not more than two quadrants.

The code detection circuit 46 and the discrimination circuit 48 discriminate the line using the sum of the color difference signal B-Y and the sum of the color difference signal R-Y within the burst section as described above.

First, the two color difference signals BY and RY output from the first and second LPFs 6 and 10 are accumulated during the burst period by the first and second accumulation circuits 40 and 42, respectively, during the burst period. Become. The burst section pulse BFP input to the third and fourth latches 14 and 22 becomes logic 1 in the burst signal section as shown in FIG. 2, and the reset signal RST is shown in FIG. The outputs of the fourth latches 14 and 22 are cleared. Accordingly, the accumulation operation proceeds only in the burst section. At this time, in the third latch circuit 14, as shown in FIG. 2, the sum SUMBY of the color difference signal BY is output at the falling point of the second clock signal CLK2, and in the fourth latch circuit 22, the color difference at the rising point of the second clock signal CLK2. The sum SUMRY of the signal RY is output. The final sum accumulated during the burst section for each line is latched to the fifth and seventh latches 16 and 24 at the falling point of the burst section pulse BFP, respectively, as shown in FIG. Here, the second clock signal CLK2 is a signal obtained by dividing the aforementioned first clock signal CLK1 by two.

At this time, the fifth latch circuit 16 latches the most significant bit representing the sign in the sum SUMBY of the accumulated color difference signal BY and outputs it as the first code bit MSBBY, and the sixth latch circuit 18 supplies the fifth latch circuit 16. Latches the first code bit MSBBY latched at every line, delays it for one line, and outputs it as the second code bit MSBPBY. The seventh latch circuit 24 latches the most significant bit representing the sign in the sum SUMRY of the accumulated color difference signal RY and outputs it as the third code bit MSBRY. The eighth latch circuit 26 includes the seventh latch circuit 24. The third code bit MSBRY latched in the latch is latched every line, delayed for one line, and output as the fourth code bit MSBPRY.

The above first to fourth code bits MSBBY, MSBPBY, MSBRY, and MSBPRY are input to the discrimination circuit 48, and finally the lines are discriminated by the discrimination circuit 48. The line discrimination signal PLINE finally output from the discrimination circuit 48 is output as logic 1 when the current processing line is determined to be an even line, and as logic 0 when the odd line is determined.

For example, if the current line is the even line and the previous line is the odd line, when 0θπ / 2, as shown in the table (5), the signs of the color difference signals BY and RY are both + and the first code bit MSBBY and the third code Bits MSBRY are all logical zeros. In addition, since the previous line is an odd line, in the table (5), the sign of the color difference signal B-Y is + and the sign of the color difference signal R-Y is-so that the second code bit MSBPBY becomes logical 0 and the fourth code bit MSBPRY becomes logical 1.

Accordingly, the output of the exclusive OR gate 28 becomes logical 0, and the output of the exclusive negative logic gate 30 also becomes logical 0, so that the output of the AND gate 32 becomes logical zero.

At this time, the line discrimination signal PLINE input to the inverter 34 represents the previous line, that is, the odd line, and thus becomes a logic zero. As a result, the output of the inverter 34 becomes logic 1, and thus the output of the exclusive logic sum gate 36 becomes logic 1. The ninth latch circuit 38 latches the output of the exclusive logic sum gate 36 by the horizontal synchronizing signal HYSNC and outputs it as the line discrimination signal PLINE. Therefore, the line discrimination signal PLINE output from the ninth latch circuit 38 becomes logic 1, indicating that the current line is an even line.

The line discrimination signal PLINE obtained as described above is inputted by the modulation / modulation carrier generating unit of the PAL type image processing apparatus, so that carriers suitable for the odd or even lines can be generated accurately, and are also input to the phase correction circuit to fit each line. Phase correction can be achieved.

As described above, the present invention improves the reliability of discrimination by accurately discriminating lines using only the sign of the color difference signal that appears during the burst section of the PAL digital video signal, and can easily implement a digital processing circuit by configuring a digital processing circuit. As a result, there is an advantage in reducing the volume of the circuit and reducing power consumption.

Claims (1)

A line discrimination circuit for discriminating a line for a PAL digital video signal, comprising: demodulation means for demodulating two color difference signals BY and RY by removing a carrier from the video signal, and two color differences demodulated during a burst section of the video signal. Code detection means for detecting a code for a processing line and a current processing line one line before each of signals BY and RY, and symbols of previous and current lines for each of the detected two color difference signals BY and RY, respectively. And a judging means for judging a current line. 2. The apparatus according to claim 1, wherein the demodulation means comprises: a multiplier 2 for multiplying the video signal by a carrier wave, a first latch circuit 4 for latching a color difference signal BY component among the output signals of the multiplier 2; A first low pass filter 6 for extracting the color difference signal BY by removing the double carrier component by lowpass filtering the color difference signal BY component latched in the first latch circuit 4, and the multiplier 2 The second latch circuit 8 latching the color difference signal RY component among the output signals of the?) And the low-pass filter of the color difference signal RY component latched to the second latch circuit 8 remove the carrier component doubled to remove the color difference. And a second low pass filter (10) for extracting the signal (RY). 3. The code of claim 2, wherein the code detecting means accumulates the color difference signal BY every line during the burst period, and the most significant bit representing a sign in the sum of the accumulated color difference signal BY. Latches and latches the fifth latch circuit 16 for outputting the first code bit and the first code bit latched in the fifth latch circuit 16 every line to delay for one line, and then to the second code bit. Latches a sixth latch circuit 18 for outputting as a second, a second accumulating circuit 42 for accumulating the color difference signal RY for each line during a burst period, and a most significant bit indicating a sign in the sum of the accumulated color difference signal RY. The seventh latch circuit 24 outputting the third code bit and the third code bit latched in the seventh latch circuit 24 every line, delaying for one line, and outputting the fourth code bit. Characterized in that the eighth latch circuit 26 A determination circuit. 4. The exclusive negative logic gate according to claim 3, wherein the discriminating means includes an exclusive logical sum gate 28 for exclusive OR of the first and second code bits and an exclusive negative logic sum of the third and fourth code bits. (30), an AND (34) for inverting the output of the exclusive OR (28) and the exclusive negative logic gate (30), and an inverter (34) for inverting the line discrimination signal for the previous line; An exclusive logic sum gate 36 exclusively ORing the outputs of the product gate 32 and the inverter 34, and an output of the exclusive logic sum gate 36 by latching the output of each of the exclusive logic sum gates 36 every line and outputting a line discrimination signal for the current line. A line discrimination circuit comprising nine latch circuits (38). 5. The first adder (12) of claim 4, wherein the first accumulator circuit (40) adds a color difference signal BY output from the first low pass filter (6) to a sum of previous color difference signals BY. And a third latch circuit 14 which latches the output of the first adder 12 and applies the common value to the first adder 12 and the fifth latch circuit 16. Circuit. 6. The second adder (20) according to claim 5, wherein the second accumulator (42) adds the color difference signal RY output from the second low pass filter 10 to the sum of previous color difference signals RY. And a fourth latch circuit 22 configured to latch the output of the second adder 20 and apply it to the second adder 20 and the seventh latch circuit 24 in common. Circuit.