JP4656915B2 - Color signal demodulator - Google Patents

Description

  The present invention relates to a burst lock circuit and a chroma killer control circuit in a color signal demodulator for television signal processing.

  In recent years, due to advances in semiconductor technology, digital processing of analog television broadcast receiving devices has evolved at the same time, and in particular, digital processing of receiving devices using common devices regardless of the broadcasting system (NTSC, PAL, SECAM, etc.) It has been regarded as important to achieve this.

Hereinafter, a conventional burst lock device will be described with reference to the drawings.
FIG. 4 is a diagram showing the overall configuration of the video demodulation device block.
In FIG. 4, a video demodulator block 401 includes a video signal input terminal 402, an A / D converter 403, a YC separator 404, a color signal demodulator 405, a luminance component signal output terminal 406, and an RY signal. An output terminal 407 and a BY signal output terminal 408 are included.

  The video signal S 402 input from the video signal input terminal 402 of the video demodulator block 401 is input to the A / D converter 403 inside the video signal demodulator block 401. In the A / D converter 403, the video signal S402 that is an analog signal is converted into a digital signal in accordance with the timing of the clock signal S405 output from the color signal demodulator 405. The clock signal S405 is a clock signal synchronized with the burst signal present in the back porch portion of the video signal S402, and has a frequency twice or more that of the burst signal according to the Nyquist sampling theorem. . Here, it is assumed that a clock signal S405 having a frequency four times that of the burst signal is generated.

  Next, a digital signal obtained by digitizing the video signal output from the A / D converter 403 is input to the YC separation device 404.

  In the YC separation device 404, the digital signal output from the A / D converter 403 is separated into a luminance component signal S404y and a color component signal S404c multiplexed in the video signal, and the luminance component signal S404y is output as a luminance component signal. The signal is output to the outside of the video demodulation device block 401 via the terminal 406. On the other hand, the color component signal S404c separated by the YC separation device 404 is output to the color signal demodulation device 405. In general, a YC separation device includes a comb filter or a notch filter and a bandpass filter.

  The color signal demodulator 405 generates a clock S405 synchronized with the burst signal and supplies it to the A / D converter 403 and the YC separator 404, and outputs the color component signal S404c output from the YC separator 404 to RY. The component signal and the BY component signal are separated and output. Thereafter, the RY component signal S407 separated by the color signal demodulator 405 is demodulated through the RY signal output terminal 407, and the BY component signal S408 is demodulated through the BY signal output terminal 408, respectively. It is output outside the device block 401.

Next, the internal structure of the color signal demodulator 405 in FIG. 4 will be described in more detail.
FIG. 5 is a block diagram showing a configuration of a conventional color signal demodulator. This color signal demodulator is configured to receive an NTSC video signal.

  In FIG. 5, a color signal demodulator 405 includes a color component signal input terminal 500, a burst gate pulse input terminal 503, a loop filter 51, a color signal multiplexing circuit 52, an RY output circuit 53, and a B- A Y output circuit 54, a 4FSC clock output terminal 513, an RY signal output terminal 518, and a BY signal output terminal 519 are included.

The color component signal input terminal 500 is an input terminal provided in the color signal demodulator 405, and a multi-bit digitized color component signal S 404 c is output to the loop filter 51 via the color component signal input terminal 500. Is done.
The loop filter 51 generates a clock signal synchronized with a burst signal having a frequency N times that of the burst signal (N is an integer of 2 or more). Here, a description will be given of generating the clock signal S405 having a frequency four times that of the burst signal. As shown in FIG. 5, the loop filter 51 includes a latch circuit 501, a gate circuit 502, an LPF 504, a constant generation circuit 505, an addition circuit 506, a ramp generation circuit 507, and a sine wave. The ROM 508, D / A converter 509, LPF 510, quadruple circuit 511, and divide-by-four circuit 512 are included.

  The L / H terminal of the flip-flop group constituting the latch circuit 501 has a signal obtained by dividing the clock signal S405 having a frequency four times that of the burst signal output from the quadrature circuit 511 by the four-frequency divider circuit 512, That is, a signal having the same frequency as the burst signal is input through the gate circuit 502. Note that the gate circuit 502 performs a logical operation on the burst gate pulse input from the burst gate pulse input terminal 503 and a signal having the same frequency as the burst signal output from the divide-by-4 circuit 512 at the timing of the burst signal. Only to supply a signal to the L / H terminal of the flip-flop group.

  The latch circuit 501 latches only the burst signal portion of the color component signal S404c at the same cycle as the burst signal at the timing when the signal is supplied to the L / H terminal of the flip-flop group constituting the latch circuit 501. Become. This results in sampling the phase error when burst locking.

  Thereafter, the phase error component at the time of burst lock sampled by the latch circuit 501 is sent to the LPF circuit 504.

  The LPF circuit 504 is a cumulative integration circuit, and integrates the phase error component sampled in the burst portion of the color component signal in S404c. As a result, if no phase error occurs, the output is zero, and the burst signal and the signal having the same frequency as the burst signal output from the divide-by-4 circuit 512 are completely both in frequency and phase. It will match and will be burst locked.

  The constant generation circuit 505 determines the center frequency when the PLL operation is performed, and outputs the center frequency when the output of the LPF 504 is non-zero, and the burst signal when the output of the LPF 504 is zero, that is, when the burst is locked. Outputs a constant value according to the frequency of.

  The adder circuit 506 generates a value obtained by adding the phase error component cumulatively integrated in the LPF 504 and the output of the constant generation circuit 505, and outputs the addition result to the ramp generation circuit 507. The ramp generation circuit 507 changes the slope of the ramp waveform in accordance with the output value from the adder circuit 506. For example, if the output value from the adder circuit 506 is large, the slope of the generated ramp becomes steeper and vice versa. If the value is small, the slope of the output ramp waveform becomes gentle.

  The output from the ramp generation circuit 507 is connected to the address of the sine wave ROM 508, and there are n addresses such as 0, 1, 2, 3,. Then, the output is configured to output an output corresponding to a sine function. That is, the ramp generation circuit 507 replaces the value of y = sin (2πx / n) with a digital value when the address input is “x” which is an arbitrary integer from 0 to n and the output is “y”. It is configured to output. With such a configuration, the address input of the sine wave ROM 508 is reproduced as a digital value because the output of the ramp generation circuit 507 is a ramp as described above, and the output of the LPF 504 is non-displayed. When it is zero, by controlling the slope of the ramp waveform, the phase can be changed so that it becomes zero, and the output from the sine wave ROM 508 has its frequency changed.

  Thereafter, the digital output from the sine wave ROM 508 is converted into an analog waveform by the D / A converter 509, and the discrete noise component of the output waveform from the D / A converter 509 is removed by the LPF 510.

  With the above configuration, a burst lock clock having the same frequency and phase as the burst signal can be generated as an output from the LPF 510.

  The output from the LPF 510 is input to the frequency multiplier 511 and multiplied by 4, and then output to the frequency divider 512, the output terminal 513 of the 4FSC clock, and the selector 515.

  The divide-by-4 circuit 512 divides the clock signal S405 having a frequency four times that of the burst signal output from the quadruple circuit 511 into four, converts it to a signal having the same frequency as the burst signal, and then sends it to the gate circuit 502. Output.

  A 4FSC clock having a frequency four times that of the burst clock output from the multiplier circuit 511 is supplied to the A / D converter 403 and the YC separator 404 from the output terminal 513 of the 4FSC clock as shown in FIG. The

Next, based on the clock signal output from the loop filter 51, the color signal multiplexing circuit 52 converts the color component signal input from the color component signal input terminal 500 into an RY component signal and a BY component signal. And outputs a signal obtained by multiplexing the RY component signal and the BY component signal at alternate timings. The color signal multiplexing circuit 52 includes a selector 515 and an inversion circuit 514 as shown in FIG.
Hereinafter, processing contents of the inverting circuit 514 and the selector 515 will be described in more detail.

In the NTSC system or PAL system broadcasting system, since the phase-modulated color component signal S404c is transmitted, for example, when the carrier signal is expressed as a sine wave,
Cin = R · sin {2πf _sc * t + φ (t)} (1)
Can be written. Note that fsc is a frequency of the burst signal and is called a so-called subcarrier frequency, and R means an amplitude. Also,
ω _sc = 2πf _sc
If the sampling frequency in the A / D converter 403 of FIG. 4, that is, the clock signal S405 is fs,
4 fsc = fs
The following relationship holds, and the sampling period T is
T = 1 / fs
It can be expressed as. Furthermore, since it operates at a frequency four times the burst clock, each sample point is
t = 4nT, (4n + 1) T, (4n + 2) T, (4n + 3) T
Can be written.
When the data of the first sample point at this time is substituted into the equation (1),
Rsin {ω _sc * (4nT) + φ (4nT)} = sin {2πf _sc * 4n / 4f _sc + φ (4nT)} = sin {2nπ + φ (4nT)}
= Rsin (φ (4nT))
Then, the term of ω _sc disappears.
Similarly, calculating for the second sample point:
Rsin {ω _sc * (4n + 1) T + φ ((4n + 1) T)} = Rsin {ω _sc * 4nT + ω _sc * T + φ ((4n + 1) T)}
The first term in Sin is 2nπ and the second term is
ω _sc * T = 2πf _sc / 4f _sc = π / 2
Because it becomes
= Rcos {φ ((4n + 1) T)} is obtained.

Organizing the above,
First sample point = Rsin (φ (4nT))
Second sample point = Rcos (φ ((4n + 1) T))
The first sample point changes to the same function format as the input signal (1), and the second sample point changes to a cosine function.

Similarly, if only the results are shown for the third and fourth sample points,
Third sample point = -Rsin (φ ((4n + 2) T))
4th sample point = -Rcos (φ ((4n + 3) T))
At the third sample point, the sign of the input signal (1) is inverted. At the fourth sample point, the sign is inverted and the cosine function is changed.

  To summarize the above results, by adopting only the first and third sample points for the input signal, an output having the same trigonometric function format as the input signal which is a sine function and a carrier signal dropped is obtained. Will be. On the other hand, the data of the second and fourth sample points have the form of a cosine function whose phase is shifted by 90 ° with respect to the input signal of the sine function used in this calculation, and an output with a carrier signal dropped is obtained. .

  For the demodulation of the NTSC signal subjected to this phase modulation, the loop filter 51 is controlled so that the sample data value corresponding to the first sample point of the burst signal becomes zero. From 515, the first and third sample data are output as RY component signals, and the second and fourth sample data are output as BY component signals. At this time, the inverting circuit 514 operates so as to invert the sign of the data value at the third sample point and the fourth sample point, and the sign of the data value at the first sample point and the third sample point. The sign of the data value of the point and the sign of the data value at the second sample point are made to coincide with the sign of the data value at the fourth sample point.

  Thus, the selector 515 multiplexes and outputs the RY component signal and the BY component signal at alternate timings.

  Thereafter, the RY component signal and the BY component signal output from the selector 515 at alternate timings are output from the RY signal output terminal 518 via the RY output circuit 53. In addition to being output to the demodulator 405, the BY component signal is output from the BY signal output terminal 519 to the color signal demodulator 405 via the BY output circuit 54.

  FIG. 6 shows a supplementary explanatory diagram. In FIG. 6, the horizontal axis indicates the phase of the BY signal, the vertical axis indicates the phase of the RY signal, and in the NTSC system, the phase of the burst signal is orthogonal to the RY axis as shown in FIG. It has characteristics parallel to the cage BY signal.

As described above, when the configuration of the conventional color signal demodulator is adopted, the demodulation axis thereof is parallel to the burst signal and the RY axis is orthogonal to the RY axis.
JP-A-4-72891

However, the above configuration has the following problems.
As a first problem, the color signal demodulating device of the conventional example can be burst-locked with respect to the NTSC signal, but cannot be burst-locked when the PAL signal is received.

The reason will be described with reference to the phase of the PAL burst signal in FIG. In FIG. 7, the horizontal axis indicates the phase of the BY signal, and the vertical axis indicates the phase of the RY signal.
As shown in FIG. 7, in the PAL system, the phase of the burst signal is shifted 90 degrees for each line and transmitted. Therefore, even if the first line is burst-locked to match the phase of the 601 burst signal, the burst signal shifts in the phase direction of 602 in the next line. Therefore, the above-described conventional color signal demodulator cannot secure a stable pull-in characteristic and cannot demodulate a PAL signal.

  In addition, in order to be able to receive and demodulate both the NTSC system and the PAL system by using a common device, it is possible to prepare a circuit dedicated to PAL that is completely independent of the NTSC system demodulator shown in the conventional example. However, when a completely independent device dedicated to PAL is prepared, the circuit scale simply increases, and the purpose of realizing the circuit scale with a common device cannot be realized.

  As a second problem, the phase of the burst signal can be made parallel to the phase axis of the RY signal in the same manner as in the NTSC system when a PAL signal is received by some method. However, since the phase axis of the PAL burst signal changes by 90 degrees for each line, there is a problem that it is necessary to always detect the phase direction of the burst signal that changes for each line. .

  That is, even under harsh conditions such as weak electric fields and burst signal level compression, the NTSC system has only constant phase information for each line, so that burst lock is lost on a specific line. Even if it falls into the abnormal state, it can be demodulated normally only by holding the phase information of the previous line. On the other hand, in the PAL system, as already described, since the burst signal shifts the phase by 90 degrees for each line, it is necessary to accurately detect the phase information. In particular, it is necessary to accurately detect the phase information about the phase direction of the burst signal, in particular whether the RY component signal of the burst signal is in the positive direction or the negative direction. . If the signal polarity called the line identity signal cannot be detected stably, color lateral noise or the like will appear on the screen of a television receiver or the like.

  The third problem is derived from a copy guard pulse inserted in a vertical blanking period of media such as a recent video decoder or DVD device.

  That is, the color signal is demodulated on the basis of the burst signal. However, when the copy guard pulse is inserted in the medium, the sync separation circuit may malfunction, and the timing at which the burst signal exists may be erroneous. . Thereby, in particular, there is a high possibility of erroneous detection of the line identity information described above. Therefore, it is necessary to further provide a countermeasure circuit in the apparatus so as to cope with a case where a copy card pulse is inserted in the medium.

  The present invention has been made in view of the above problems, and performs reception and demodulation of signals by the NTSC system and the PAL system even in a weak electric field or under degradation conditions such as burst compression with a relatively simple circuit configuration. It is an object of the present invention to provide a color signal demodulator that enables the above.

In order to solve the above problems, color signal demodulating device of the present application, the clock signal delayed by 90 degrees with respect to the quantized signal clock signal synchronized with the color component signals in the burst signal is the corresponding clock phase And a clock timing changing unit that selectively outputs the signal based on the polarity of the RY component signal of the PAL signal, and is synchronized with a burst signal having a frequency N times that of the burst signal (N is an integer of 2 or more). A loop filter that generates and outputs the generated clock signal; and, based on the clock signal output from the loop filter, separates the color component signal into an RY component signal and a BY component signal; A color signal multiplexing unit that outputs a signal obtained by multiplexing the component signal and the BY component signal at alternate timings, and a phase of the multiplexed signal output from the color signal multiplexing unit , The RY component of the PAL system signal, and a calculation unit that performs a correlation calculation process between the multiplexed signal and the 1H delayed signal obtained by delaying the multiplexed signal by one period of the horizontal synchronization signal. Based on the polarity of the signal, an RY inversion unit for selectively switching the polarity of the RY component signal of the signal output from the arithmetic unit, and an RY inversion from the RY inversion unit An RY output unit that outputs a Y component signal and a BY output unit that outputs a BY component signal of a signal output from the arithmetic unit are provided.
This makes it possible to receive and demodulate a PAL signal using a color demodulator that demodulates an NTSC signal.

Also, color signal demodulating device of the present application, in the color signal demodulating device, when the received signal is a signal of the NTSC system, the clock timing change portion having the said loop filter, a clock signal synchronized with the burst signal The RY output unit and the BY output unit directly receive the multiplexed signal output from the color signal multiplexing unit, and input the RY output unit and the BY output unit. The RY component signal and the BY component signal are output from the -Y output unit, respectively.
This makes it possible to receive and demodulate both the NTSC system and the PAL system with a common device, and to realize a reduction in the circuit scale of the color signal demodulator.

Also, color signal demodulating device of the present application, in the color signal demodulation apparatus, the arithmetic unit includes a 1H delay section for delaying one cycle of the multiplex signal of the horizontal synchronizing signal output from the color signal multiplexing unit A phase axis rotation unit that rotates the phase axis of the multiplexed signal from the color signal multiplexing unit and the multiplexed signal delayed by the 1H delay unit by 45 degrees, respectively, and the phase axis is converted by the phase axis rotation unit. The color signal multiplexing unit includes a correlation calculation unit that calculates the correlation between the multiplexed signal from the color signal multiplexing unit and the multiplexed signal from the 1H delay unit.
This makes it possible to demodulate a PAL signal whose phase axis is inclined by 45 degrees with respect to the phase axis of the NTSC signal.

Also, color signal demodulating device of the present application, the in color signal demodulation apparatus, the phase axis rotation unit, wherein the color signal multiplexed signal output from the multiplexing unit and multiplexing signals output from the 1H delay unit Are delayed by one cycle of the clock signal output from the loop filter to the color signal multiplexer, the multiplexed signal output from the color signal multiplexer, and the 1T delay A first addition unit that adds the multiplexed signal from the color signal multiplexing unit delayed by 1T by the unit, a multiplexed signal output from the color signal multiplexing unit, and a 1T delay by the 1T delay unit A first subtracting unit that performs a difference process with the multiplexed signal from the color signal multiplexing unit, the multiplexed signal output from the 1H delay unit, and the 1H delayed by 1T by the 1T delay unit Many from the delay section Differential processing of the second adder for adding the multiplexed signal, the multiplexed signal output from the 1H delay unit, and the multiplexed signal from the 1H delay unit delayed by 1T by the 1T delay unit A second subtracting unit, wherein the correlation calculating unit performs a difference process between the output from the first adding unit and the output from the second adding unit, It is characterized by comprising a third addition unit that performs an addition process of the output from the first subtraction unit and the output from the second subtraction unit.
As a result, it is possible to realize demodulation of a PAL signal whose phase axis is inclined 45 degrees with respect to the phase axis of the NTSC signal with a simple configuration without using a multiplier.

Also, color signal demodulating device of the present application, in the color signal demodulation apparatus, the arithmetic unit includes a phase axis rotation unit for rotating 45 degrees each phase axis of the multiplexed signal from the chrominance signal multiplexing unit, wherein A 1H delay unit that delays a multiplexed signal output from the phase axis rotation unit by one cycle of a horizontal synchronization signal, a multiplexed signal output from the phase axis rotation unit, and a multiplexed signal output from the 1H delay unit And a correlation calculation unit for calculating the correlation.
This makes it possible to demodulate a PAL signal whose phase axis is inclined by 45 degrees with respect to the phase axis of the NTSC signal.

Also, color signal demodulating device of the present application, in the color signal demodulation apparatus, the phase axis rotation unit, the multiplexed signal output from the color signal multiplexing unit, the color signal multiplexing unit from said loop filter The first 1T delay unit that delays the clock signal that is output by 1 cycle, the multiplexed signal output from the color signal multiplexing unit, and the color signal multiplexing unit delayed by 1T by the 1T delay unit A first addition unit for adding the multiplexed signals from the color signal multiplexing unit, a multiplexed signal output from the color signal multiplexing unit, and a multiplexing from the color signal multiplexing unit delayed by 1T by the 1T delay unit A first subtracting unit that performs a difference process with the signal, and the 1H delay unit delays the output from the first adding unit and the first subtracting unit by one period of a horizontal synchronization signal, The correlation calculation unit is configured to perform the first addition. A third subtractor that performs a difference process between the output from the first adder delayed by the 1H delay unit, the output from the first subtractor, and the 1H delay unit And a third addition unit for performing addition processing with the output from the first subtraction unit delayed by the above.
As a result, it is possible to realize demodulation of a PAL signal whose phase axis is inclined 45 degrees with respect to the phase axis of the NTSC signal with a simple configuration without using a multiplier.

Also, color signal demodulating device of the present application, the in color signal demodulation apparatus, the rotation signal of the phase axis of the multiplexed signal output from the color signal multiplexing unit, the PAL system signals R-Y component signals A signal indicating the polarity of the RY component signal of the PAL system signal from the first line identity detection section for detecting a line identity signal which is a signal indicating the polarity of the PAL signal and the signal output from the correlation calculation section And a second line identity detection unit for detecting a line identity signal, wherein the loop filter is an RY component signal of a PAL signal output from the first line identity detection unit. The clock signal synchronized with the burst signal and the clock signal delayed by 90 degrees with respect to the phase of the clock are selectively output based on the signal indicating the polarity of the signal, and the RY inversion is performed. Is based on a signal indicating the polarity of the RY component signal of the PAL signal output from the second line identity detector, and the RY component signal of the signal output from the correlation calculator is The polarity is selectively switched and output.
As a result, the first line ID detection unit can detect the line ID signal without being affected by the output signal from the 1H delay unit. Even under severe conditions such as the above, it is possible to stably detect the line identity signal from the first line identity detection unit.

Also, color signal demodulating device of the present application, the in color signal demodulation apparatus, the second line Ai dent detection unit, from the signal outputted from the correlation calculation unit, the PAL system signals R-Y component signals A sign detection unit that detects the polarity of the signal and outputs a signal indicating the detected polarity, and a signal generation unit that outputs a signal generated so that a different polarity is indicated at each timing when the horizontal synchronization signal is input When the control signal from the inversion control unit for instructing the inversion of the signal is input, the generated signal is inverted and output from the protection line identity signal generation unit and the sign detection unit. A match determination unit that determines whether the polarity indicated by the signal matches the polarity indicated by the signal output from the protection line identity signal generation unit by a period of a horizontal synchronization signal, and the match determination unit As a result of the determination, if a mismatch state between the polarity indicated by the signal output from the code detection unit and the polarity indicated by the signal output from the protection line identity signal generation unit has accumulated a predetermined number of times, An inversion control unit that outputs a control signal that instructs the protection line identity signal generation unit to invert the signal; and an output terminal that outputs an output signal from the protection line identity signal generation unit as a line identification signal It is characterized by having.
This makes it possible to always detect line-identity signals stably even when receiving signals using the PAL method, and to apply color lateral noise on the screen of television receivers even under severe deterioration conditions such as in weak electric fields. Stable demodulation can be realized without generating.

Also, color signal demodulating device of the present application, in the color signal demodulating device, the second line Ai dent detection unit counts the number of horizontal synchronizing signal inputted between the vertical synchronization signal, is the regimen numeric It further includes an inversion function stop unit that invalidates the control signal output from the inversion control unit until it exceeds a preset value.
This makes it possible to operate the second line identity detector at a timing excluding the influence of the copy guard pulse.

Also, color signal demodulating device of the present application, in the color signal demodulating device, the second line Ai dent detector indicating the polarity of the R-Y component signal of the signal of the PAL system to the R-Y reversing unit The second line identity detection unit detects the polarity of the RY component signal of the PAL signal from the signal output from the calculation unit, and outputs a signal indicating the detected polarity A detection unit and a signal generation unit that outputs a signal generated so as to indicate a different polarity at each timing when a horizontal synchronization signal is input, and a control signal from an inversion control unit that instructs the inversion of the signal When input, a protection line identity signal generation unit that inverts and outputs the generated signal, a polarity indicated by a signal output from the code detection unit, and an output from the protection line identity signal generation unit A coincidence determination unit that determines whether or not the polarity indicated by the signal coincides with the period of the horizontal synchronization signal, and the polarity indicated by the signal output from the code detection unit as a result of determination by the match determination unit; Control for instructing the protection line identity signal generation unit to invert the signal when the inconsistency with the polarity indicated by the signal output from the protection line identification signal generation unit has accumulated a predetermined number of times. An inversion control unit that outputs a signal and an output terminal that outputs an output signal from the protection line identity signal generation unit as a line identity signal are provided.
This makes it possible to always detect line-identity signals stably even when receiving signals using the PAL method, and to apply color lateral noise on the screen of television receivers even under severe deterioration conditions such as in weak electric fields. Stable demodulation can be realized without generating.

Also, color signal demodulating device of the present application, in the color signal demodulating device, the second line Ai dent detection unit counts the number of horizontal synchronizing signal inputted between the vertical synchronization signal, is the regimen numeric It further includes an inversion function stop unit that invalidates the control signal output from the inversion control unit until it exceeds a preset value.
This makes it possible to operate the second line identity detector at a timing excluding the influence of the copy guard pulse.

  According to the color signal demodulator according to the present invention, first, it is possible to receive and demodulate both the NTSC system and the PAL system with a common device. Secondly, it is possible to detect a stable line-identity signal stably in the reception of the PAL broadcasting system, and the color on the screen of a television receiver or the like even under severe deterioration conditions such as in a weak electric field. It is possible to stably demodulate without generating horizontal noise. Furthermore, as a third effect, even when a copy guard pulse is inserted in media such as a video decoder or a DVD device, even if the sync separation circuit is affected by the influence and malfunctions, the line identification can be stably performed. Signals can be detected and complemented.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(Embodiment 1 of the invention)
The color signal demodulator according to the first embodiment of the present invention is able to demodulate not only the NTSC system but also the PAL system color signal by using the color signal demodulator shown in FIG. Is.

  FIG. 1 is a block diagram showing an example of the configuration of a color signal demodulator according to Embodiment 1 of the present invention, FIG. 6 is a diagram showing the phase of an NTSC burst signal, and FIGS. 7 and 8 are PAL schemes. It is a figure which shows the phase of this burst signal.

  1, the color signal demodulator according to Embodiment 1 of the present invention includes a color component signal input terminal 500, a burst gate pulse input terminal 503, a loop filter 1, a color signal multiplexing circuit 52, and an arithmetic circuit 2. The first line identity detection circuit 3, the second line identity detection circuit 4, the RY inversion circuit 5, the RY output circuit 53, the BY output circuit 54, and the 4FSC clock. Output terminal 513, RY signal output terminal 518, and BY signal output terminal 519. In FIG. 1, the same components as those of the conventional color signal demodulator shown in FIG. 5 are denoted by the same reference numerals, and description thereof is omitted here.

  The loop filter 1 is different from the loop filter 51 of FIG. 5 in that the clock signal synchronized with the burst signal and the clock signal delayed by 90 degrees with respect to the phase of the clock are based on the polarity of the RY component signal of the PAL system signal. And a clock timing changing circuit 11 for selectively outputting the same.

  Thus, depending on whether or not the clock timing changing circuit 11 is operated, the loop filter 1 causes the clock signal synchronized with the burst signal having a frequency N times (N is an integer of 2 or more) of the burst signal, and the clock It is possible to generate and output a clock signal in which the signal is shifted by 90 degrees for each line of the PAL signal.

Hereinafter, the clock timing changing circuit 11 included in the loop filter 1 will be described in more detail.
The clock timing change circuit 11 includes a selector 100 and an IT delay circuit 101.
The selector 100 selects and outputs the output from the 1T delay circuit 101 and the output from the divide-by-4 circuit 512 based on S3 output from the first line identity detection circuit 3.

  The 1T delay circuit 101 delays one clock having the same frequency as the burst signal output from the divide-by-4 circuit 512 and delays the phase of the burst signal output from the divide-by-4 circuit by 90 degrees. Circuit.

  Here, the first line identity detection circuit 3 is a signal in which the polarity of the RY component signal of the PAL signal is a positive signal as indicated by 601 in FIG. 7, or 602 in FIG. It detects whether the signal is in the negative direction as shown in FIG.

  In the present embodiment, the first line identity detection circuit 3 is a signal of the R-Y axis component output from the adder 104 whose phase axis has been rotated by a first phase axis rotation circuit 22a described later. The burst gate pulse input input from the burst gate pulse input terminal 503 is input, and the sign of the RY axis component signal output from the adder 104 is used as the burst gate input from the burst gate pulse input terminal 503. It is determined that the pulse is enabled, that is, while the burst signal is present, and the value is held when the burst gate pulse is disabled. Then, the first line identity detection circuit 3 outputs a flag indicating the polarity of the RY component signal of the detected burst signal to the selector 100 as S3. The flag indicating the phase direction is generally called a PAL line-ident signal.

  However, the line ID signal output from the first line ID detection circuit 3 is not limited to the output from the adder 104, but the output from the adder 108 of the second phase axis rotation circuit 22b or the correlation calculation. It is also possible to calculate using the output from the subtracter 110 of the circuit 32. However, if the line identity signal detected for burst lock is not taken from the output of the adder circuit 104, sufficient characteristics cannot be obtained under severe conditions such as in a weak electric field or burst signal level compression. The reason is that when the first line identifier information is obtained from the output from the adder 108 of the second phase axis rotation circuit 22b, the 1H delay circuit 21 delays the horizontal synchronization signal by one period. Is used for loop control for burst lock, so that a stationary phase error occurs. Also, when the burst lock is performed using the output from the subtractor 110 of the correlation calculation circuit 32, the output from the subtractor 110 of the correlation calculation circuit 32 is output from the adder 108 of the second phase axis rotation circuit 22b. Therefore, a steady phase error occurs as in the case of using the output from the adder 108 of the second phase axis rotation circuit 22b, and the burst lock performance is deteriorated. is there.

  By the way, in the conventional color signal demodulating apparatus described with reference to FIG. 5, the flip-flop group 501 is used as a starting point, passes through the quadruple circuit 511, and finally returns to the load hold input of the flip-flop group 501. A loop filter is configured. Therefore, in the NTSC system, the burst clock signal in S405 is a clock that maintains a phase parallel to the burst signal as shown in FIG. On the other hand, in the PAL system, as shown in FIG. 7, a clock is obtained by shifting the phase of the burst signal by 90 degrees for each line.

Therefore, in the color signal demodulator according to Embodiment 1 of the present invention, as described above, the clock timing changing circuit 11 including the selector 100 and the IT delay circuit 101 is provided, and when the PAL system signal is received, Based on the flag S3 indicating the polarity of the RY component signal of the burst signal output from the first line identity detection circuit 3, a signal synchronized with the burst signal output from the divide-by-4 circuit 512, and a 1T delay A signal delayed by 90 degrees with respect to the phase of the burst signal output from the circuit 101 is switched and output.
As a result, the loop filter 1 makes it possible to perform a burst lock while ensuring a stable pull-in characteristic of a PAL signal in a form in which the phase of the burst signal is shifted 90 degrees for each line.

  Note that the latch circuit 501, the gate circuit 502, the LPF 504, the constant generation circuit 505, the addition circuit 506, the ramp generation circuit 507, the sine wave ROM 508, the D / A converter 509, the LPF 510, the 4 × multiplication circuit 511, and the loop circuit 1 The divide-by-4 circuit 512 is the same as that described with reference to FIG.

  When the burst lock is performed by using the selector 100 of the loop filter 1 and the 1T delay circuit 101 to shift the phase of the burst signal by 90 degrees for each line, the input color component signal 404c is shown in FIG. The burst lock is performed as if the RY and BY axes are rotated by 45 degrees.

  That is, as shown in FIG. 8, when a color component signal 404c composed of a specific color signal vector 603 is input, the RY axis is as if it were the (RY) 'axis, and the BY axis was Since it is considered that the color component signal 404c is demodulated because it is shifted by 45 degrees with respect to the (BY) 'axis, the PAL system is obtained by demodulating it back to the original axis. Can be demodulated.

The PAL system signal demodulation processing will be specifically described below.
The arithmetic circuit 2 rotates the phase axis of the multiplexed signal output from the color signal multiplexing circuit 52 by 45 degrees, and delays the multiplexed signal and the multiplexed signal by one cycle of the horizontal synchronization signal. As shown in the figure, it comprises a 1H delay circuit 21, a first phase axis rotation circuit 22a, a second phase axis rotation circuit 22b, and a correlation calculation circuit 32. .

The 1H delay circuit 106 is a circuit component that delays the output from the selector 515 by the time of the horizontal synchronization period. In general, it is usually constituted by a memory or the like.
The first phase axis rotation circuit 22a and the second phase axis rotation circuit 22b rotate the phase axis of the input signal by 45 degrees, respectively, and include 1T delay circuits 103 and 107, and an adder 104, respectively. , 108 and subtractors 105 and 109.
The correlation calculation circuit 32 performs a correlation calculation process over two cycles of the horizontal synchronization signal, which is necessary when demodulating a PAL system signal. The correlation calculation circuit 32 includes a subtractor 110 and an adder 111. Yes.

Next, specific processing contents of the arithmetic circuit 2 will be described.
From the selector 515 shown in FIG. 1, in the case of an NTSC signal, an RY component signal (hereinafter referred to as a V signal) and a BY component signal (hereinafter referred to as a U signal) as described in the conventional example. Are alternately multiplexed and output. On the other hand, when a PAL signal is received, the phase is shifted by 45 degrees compared to the original V signal and the original U signal, as shown in FIG. And the U 'signal are alternately multiplexed and output. For this reason, when a PAL signal is received, the arithmetic circuit 2 rotates the phase axis by 45 degrees and restores the original axis to perform demodulation.

In general, rotation of the phase axis by 45 degrees can be realized by performing the calculations shown in the equations (2) and (3).
U = cos (π / 4) * U '-sin (π / 4) * V' = K (U'-V ') (2)
V = sin (π / 4) * U '+ cos (π / 4) * V' = K (U '+ V') (3)
Here, K = 2 / √2.

  The arithmetic processing of the equations (2) and (3) is performed by 1T delay circuits 103 and 107 constituting the first phase axis rotation circuit 22a and the second phase axis rotation circuit 22b, the adder 104, 108 and the subtractors 105 and 109 are realized as follows.

First, the processing of the 1T delay circuit 103, the adder 104, and the subtractor 105 constituting the first phase axis rotation circuit 22a will be described.
The 1T delay circuit 103 delays one cycle of the clock signal used when the U ′ signal and the V ′ signal are alternately output from the color signal multiplexing circuit 52 including the inverting circuit 514 and the selector 515. Yes, here, it is delayed by one shot in the period of the 4 fsc clock signal having a frequency four times that of the burst signal.

  The adder circuit 104 is a circuit that performs an addition process of the output from the selector 515 and the output from the 1T delay circuit 103, and the adder circuit 104 realizes an operation of (U ′ + V ′). The subtraction circuit 105 is a circuit that performs a subtraction process between the output from the selector 515 and the output from the 1T delay circuit 103, and the subtraction circuit 105 realizes an operation of (U′−V ′).

  Thereby, the first phase axis rotation circuit 22a can perform the arithmetic processing of the above formulas (2) and (3). Here, in the comparison between the equations (2) and (3) and FIG. 1, there is no circuit configuration for multiplying by K corresponding to the equations (2) and (3). In the case of the PAL system signal, as described above with reference to FIGS. 7 and 8, since the burst lock is applied while being inclined by 45 degrees with respect to the RY axis and the BY axis. , Cos (π / 4) = sin (π / 4) = √2 / 2, so that at the output stage from the selector 515, a signal that has already been compressed to a level of √2 / 2 is output. Because it becomes.

Next, the processing of the 1T delay circuit 107, the adder 108, and the subtractor 109 constituting the second phase axis rotation circuit 22b will be described. These are the 1T delay constituting the first phase axis rotation circuit 22a. The circuit 103, the adder 104, and the subtractor 105 perform exactly the same processing. The difference is that the operations of the expressions (2) and (3) are performed on the 1H delay circuit element of the 1H delay circuit 106. It is the point which is given.
This is because when the PAL system signal is demodulated, a correlation calculation process over two cycles of the horizontal synchronization signal is required, and the subtraction circuit 110 and the addition circuit 111 constituting the correlation calculation circuit 32 perform this operation. Correlation calculation of two horizontal synchronization periods is performed.

With the above configuration, after the operations (2) and (3) are completed and the correlation calculation processing is performed, the U signal, that is, the BY component signal is output from the adder circuit 111, and the V signal, that is, R A −Y component signal is output from the subtraction circuit 110.
Note that the V signal output from the subtraction circuit 110 is output with the polarity inverted for each line due to the influence of the burst signal that is inverted for each line. Therefore, here, the RY inversion circuit 5 including the inversion circuit 112 and the selector 113 is provided, and the V signal output from the subtraction circuit 110 based on the output result from the second line identity detection circuit 4 is provided. It is determined whether or not to invert the amplitude polarity of the RY inversion circuit 5 and is operated as the RY inversion circuit 5 that performs the inversion processing of the amplitude polarity of the V signal as necessary.

Here, the second line identity detection circuit 4 is such that the polarity of the RY component signal of the PAL signal is a signal in the positive direction as indicated by 601 in FIG. 7, or 602 in FIG. It detects whether the signal is in the negative direction as shown in FIG.
In the present embodiment, the second line identity detection circuit 4 determines whether the output from the subtraction circuit 110 is positive or negative during the burst signal period, outputs the result, and outputs the second line identity detection information. Is output. Thus, the second line identity detection circuit 4 outputs the output from the inverting circuit 112 to the selector circuit 113 when the RY signal output from the subtraction circuit 110 is inverted and output. If the RY signal is not inverted, the selector circuit 113 can be instructed to select a signal that is not inverted as an output.

  Next, the RY signal output of the selector 113 is output from the RY signal output terminal 518 to the outside of the color signal demodulator 405 via the RY output circuit 53. The BY signal output of the adder circuit 111 is output from the BY signal output terminal 519 to the outside of the color signal demodulator via the BY output circuit 54.

  As described above, according to the color signal demodulator according to the first embodiment of the present invention, the color component signal 404c is burst in a state where the phase is shifted by 90 degrees for each line to the conventional NTSC color signal demodulator. The clock timing changing circuit 11 to be locked and the phase axis rotation circuits 22a and 22b for performing the phase axis rotation calculation are provided so that the phase axis of the burst signal can be converted. 5 can be used to demodulate the PAL color signal. Further, in this configuration, the selector circuit 100 is controlled so as to always select a path that does not pass through the 1T delay circuit 101 of the clock timing changing circuit 11 based on the output of the first line identifier detection circuit 3 and the selector circuit. The color signal demodulator 405 shown in FIG. 5 is suitable for receiving an NTSC video signal as a circuit structure by outputting the output of 515 directly to the RY output circuit 53 and the BY output circuit 54. The color signal can be demodulated using a common device regardless of the broadcasting system such as NTSC and PAL, and the circuit scale of the color signal demodulator can be reduced. .

  In the first embodiment of the present invention, after the arithmetic circuit 2 generates the 1H delay signal by the 1H delay circuit 21, the phase axis rotation circuits 22a and 22b receive the output from the color signal multiplexing circuit 52 and the 1H delay circuit. In the above description, the phase axis rotation calculation is performed on the output from 21 and the correlation between the two signals is calculated by the correlation calculation circuit 32. However, the configuration of the calculation circuit 2 is not limited to this configuration. After the phase axis rotation circuit performs the phase axis rotation calculation on the output from the signal multiplexing circuit 52, the 1H delay circuit 21 generates a 1H delay signal, and the output from the phase axis rotation circuit and the 1H delay circuit 21 The correlation calculation circuit 32 may calculate the correlation between the two signals using the output from. In this case, since only one phase axis rotation circuit is required, the circuit scale can be reduced.

(Embodiment 2 of the invention)
Next, as a second embodiment of the present invention, the configuration of the second line identity detection circuit 4 of the color signal demodulator described in the first embodiment will be described.

FIG. 2 is a diagram showing an example of the configuration of the second line identity detection circuit 4 of the color signal demodulator according to the second embodiment of the present invention.
In FIG. 2, the second line identity detection circuit 4 includes a horizontal synchronization signal input terminal 201, an RY component signal input terminal 202, a burst gate pulse input terminal 203, a sign detection circuit 204, a protection line eye. It comprises a dent signal generation circuit 6, an EOR gate 210 that operates as a coincidence determination circuit, an inversion control circuit 7, and a line ident signal output terminal 209. A horizontal synchronization signal is input from the horizontal synchronization signal input terminal 201, an output of the subtraction circuit 110 in FIG. 1 is input from the RY component signal input terminal 202, and a burst gate pulse input terminal 203 is further input. A burst gate pulse signal is input from the burst gate pulse input terminal 503 in FIG.

  The sign detection circuit 204 operates as a line identity detection circuit. When the burst gate pulse input from the burst gate pulse input terminal 203 is enabled, the sign of the signal input from the RY component signal input terminal 202 is enabled. For a certain period, that is, a period in which a burst signal exists, and when the burst gate pulse is disabled, the value is held. With this configuration, the RY axis component of the burst signal is input from the RY component signal input terminal 202. As a result, during the burst signal period, the vector of the burst signal has a positive or negative direction. Some line identification information is output from the code detection circuit 204.

  However, this line identity information generated by using the output from the arithmetic circuit 2 shown in FIG. 1 may be erroneously detected under severe conditions such as a weak electric field or burst signal level compression. As a result, color lateral noise appears on the screen of the television receiver. Therefore, the second line identity detection circuit 4 of the color signal demodulator according to Embodiment 2 of the present invention further includes a protection line identity signal generation circuit 6, an EOR gate 210, and an inversion control circuit 5.

Based on the control signal output from the inversion control circuit 7, the protection line identity signal generation circuit 6 outputs a signal indicating a different polarity at each timing when the horizontal synchronization signal is input from the horizontal synchronization signal input terminal 201. Is.
The protection line identity signal generation circuit 6 includes, for example, a flip-flop 205, a flip-flop 206, a logic gate 207, and an EOR gate 208 as shown in the figure.

  The flip-flop 205 is a toggle flip-flop, and functions as a signal generation circuit that repeats inversion every time a horizontal synchronization signal is input from the horizontal synchronization signal input terminal 201. The flip-flop 206 is a toggle flip-flop that performs inversion at the timing when the control signal from the inversion control circuit 7 is input to the logic gate 207.

  The EOR gate 208 receives the output signal from the flip-flop 205 and the output signal from the flip-flop 206, and inverts each time a horizontal synchronization signal that is inversion controlled by the control signal from the inversion control circuit 7 is input. A signal that repeats is output. Note that the signal generated by the protection line ident signal generation circuit 5 is output as a line ident signal via the line ident signal output terminal 209.

  The EOR gate 210 is a coincidence determination circuit that determines whether the signal output from the sign detection circuit 204 and the signal output from the EOR gate 208 match or do not match with the period of the horizontal synchronization signal. Here, when the signal output from the sign detection circuit 204 and the signal output from the EOR gate 208 match, a value of “0” is output, and conversely, when the signal does not match, “1”. "Is output.

When the inconsistency between the signal output from the sign detection circuit 204 and the signal output from the EOR gate 208 has accumulated a predetermined number of times, the inversion control circuit 7 protects the protection line identifier signal generation circuit 6. A control signal for instructing the inversion of the signal is output.
The inversion control circuit 7 includes, for example, an up / down counter 211, an upper limiter detection circuit 212, a lower limiter detection circuit 213, and a logic gate 214 as shown in the figure.

  The up / down counter 211 receives the output from the EOR gate 210, which is a coincidence determination circuit, and, if the output from the EOR gate 210 is coincident, cumulatively adds the number of occurrences of coincidence in the period of the horizontal synchronization signal. Has a function of reducing the cumulative number. Here, when the signal output from the sign detection circuit 204 and the signal output from the EOR gate 208 coincide with each other from the EOR gate 210 which is a coincidence determination circuit, “0”, and when they do not coincide with each other. Since “1” is output, up-counting is performed when the output from the EOR gate 210 is “0”, and down-counting is performed when the output is “1”.

The upper limiter detection circuit 212 and the lower limiter detection circuit 213 output a signal when the count value of the up / down counter 211 exceeds a preset threshold value.
Specifically, the coincidence state between the signal output from the code detection circuit 204 and the signal output from the EOR gate 208 continues, and the count value of the up / down counter 211 is set in advance by the upper limit limiter detection circuit 212. When the threshold value is exceeded, a control signal is output from the upper limiter detection circuit 212, and the up / down counter 211 that receives the control signal via the logic gate 214 sets the upcount to the upper limiter detection circuit 212. Stop at a predetermined threshold.

  On the other hand, the mismatch state between the signal output from the sign detection circuit 204 and the signal output from the EOR gate 208 continues, and the count value of the up / down counter 211 has a threshold set in advance in the lower limiter detection circuit 213. When it exceeds, the control signal is output from the lower limiter detection circuit 213, and the up / down counter 211 receiving the control signal via the logic gate 214 sets the downcount to the lower limiter detection circuit 213. Stop at the threshold. Further, the control signal is output to the logic gate 207 as a control signal instructing inversion of the signal output from the protection line identity signal generation circuit 6.

  Then, the inversion control circuit 7 configured as described above performs inversion control of the signal output from the protection line identity signal generation circuit 6, and the signal output from the sign detection circuit 204 and the output from the EOR gate 208. To be matched with the signal to be transmitted. As a result, it is possible to supply a line ident signal that is consistent with the line ident signal detected by the code detection circuit 204.

  That is, the operation under severe conditions such as weak electric field and burst signal level compression will be described. For example, when the detection line identity signal is normal for each period of the horizontal synchronization signal, 0, 1, 0 , 1,... Should be input alternately, but because of the operation under severe conditions such as weak electric field and burst signal level compression, 0, 1, 0, 0, 0,.・ ・ Incorrect signals may occur at a certain timing. However, according to the second line identity detection circuit 4 according to the present invention, the signal output from the protection line identity signal generation circuit 5 is alternated in the period of the horizontal synchronization signal, so that it is partially incorrect. Even when the signal is generated, the original line ident signal is stably output from the line ident signal output terminal 209. When the effect was actually confirmed in a weak electric field state by experiment, it was confirmed that a performance difference of 12 dBμ occurred before and after the circuit was inserted.

  As described above, according to the color signal demodulator according to the second embodiment of the present invention, the second line identity detection circuit 4 as shown in FIG. 2 is provided to detect the phase direction of the burst signal and to In such a case, the correction is made so that the line identity signal can always be detected stably even when receiving the signal by the PAL system, and the television receiver can be used even under severe deterioration conditions such as in a weak electric field. Thus, stable demodulation can be realized without generating color lateral noise on the screen.

(Embodiment 3 of the invention)
As a third embodiment of the present invention, another configuration of the second line identity detection circuit 4 of the color signal demodulator described in the first embodiment will be described.
In the second line identity detection circuit 4 of the color signal demodulator described in the third embodiment of the present invention, in particular, a copy guard pulse is inserted in the vertical blanking period by a medium such as a recent video decoder or DVD device. This is a countermeasure for the problem that comes from being sometimes.

  That is, the color signal is demodulated based on the burst signal, but when the copy guard pulse is inserted, the sync separation circuit malfunctions and supplies the timing at which the burst signal exists at an incorrect timing. In some cases, erroneous detection of line identification information may occur. Therefore, there is a demand for a circuit that takes measures against this malfunction, and the second line identity detection circuit 4 shown in FIG. 3 is configured to provide this.

FIG. 3 is a diagram showing an example of the configuration of the second line identity detection circuit 4 of the color signal demodulator according to Embodiment 3 of the present invention.
In FIG. 3, the second line identifier detection circuit 4 includes a horizontal synchronization signal input terminal 201, an RY component signal input terminal 202, a burst gate pulse input terminal 203, a sign detection circuit 204, a protection line eye. It consists of a dent signal generation circuit 6, an EOR gate 210 that operates as a coincidence determination circuit, an inversion control circuit 7, a line ident signal output terminal 209, a vertical synchronization signal input terminal 302, and an inversion function stop circuit 8. The same components as those of the second line identity detection circuit 4 described with reference to FIG. 2 in the second embodiment are denoted by the same reference numerals, and description thereof is omitted here.

The second line identity detection circuit 4 of the color signal demodulator according to the third embodiment of the present invention is further inverted in addition to the components of the second line identity detection circuit 4 described in the second embodiment. A function stop circuit 8 is provided.
The inversion function stop circuit 8 counts the number of horizontal synchronization signals input between the vertical synchronization signals, and outputs the control signal output from the inversion control circuit 7 until the count value exceeds a preset value. It is to be invalidated.
The inversion function stop circuit 8 includes, for example, a counter 303, a coincidence detection circuit 304, and an SR flip-flop 305 as shown in the figure.

Hereinafter, the inversion function stop circuit 8 will be described in more detail with reference to FIG.
In FIG. 3, a counter 303 is a multi-bit counter that counts at the timing of the horizontal synchronization signal input from the horizontal synchronization signal input terminal 201, and receives a vertical synchronization signal input from the vertical synchronization signal input terminal 302. The count value is cleared at the timing.

  The coincidence detection circuit 304 has a function of outputting a flag indicating a coincidence when the value outputted from the counter coincides with a preset value. The preset value is a value from the timing at which the vertical synchronization signal is input to the timing at which the synchronization separation circuit is stabilized based on the period of the horizontal synchronization signal.

  The SR flip-flop 305 holds and outputs a low level when a signal is input to the input R input, that is, when a vertical synchronization signal is input from the vertical synchronization signal input terminal 302 in FIG. Further, a flag indicating a match is output from the match detection circuit 304, and when an event occurs in the S input of the SR flip-flop 305, it is inverted and a high level is output.

  As a result, immediately after the vertical synchronization signal is input, at the timing at which synchronization is easily disturbed due to the influence of a copy guard pulse or the like, the SR flip-flop 305 goes low and always keeps the gate of the logic gate 207 closed. The output from the lower limiter circuit 213 of the inversion control circuit 6 can be invalidated. On the other hand, when the coincidence detection circuit 304 outputs a flag indicating that the value matches a preset value, the SR flip-flop 305 goes high and opens the gate of the logic gate 207, and the lower limiter of the inversion control circuit 6. The output from circuit 213 can be validated.

  As described above, according to the color signal demodulating device according to the third embodiment of the present invention, the function of counting the number of horizontal synchronizing signals input between the vertical synchronizing signals in the second line identity detecting circuit 4 is also provided. And providing an inversion function stop circuit 8 that prevents the signal output from the protection line identity signal generation circuit from being inverted until the count value exceeds a preset value. The second line identity detection circuit 4 can be operated at a timing excluding the influence of the pulse.

  The present invention makes it possible to receive and demodulate signals by the NTSC system and the PAL system even under weak electric fields or under degradation conditions such as burst compression.

1 is a block diagram showing an example of the configuration of a color signal demodulator according to Embodiment 1 of the present invention. The figure which shows an example of a structure of the 2nd line identity detection circuit of the color signal demodulation apparatus by Embodiment 2 of this invention. The figure which shows an example of a structure of the 2nd line identity detection circuit of the color signal demodulation apparatus by Embodiment 3 of this invention. The figure which shows the whole structure of a video demodulation apparatus block Block diagram showing the configuration of a conventional color signal demodulator The figure which shows the phase of the burst signal of NTSC system The figure which shows the phase of the burst signal of a PAL system The figure which shows the state when the burst signal has shifted to the positive direction in the PAL system

Explanation of symbols

DESCRIPTION OF SYMBOLS 1, 51 Loop filter 2 Arithmetic circuit 3 1st line ident detection circuit 4 2nd line ident detection circuit 5 RY inversion circuit 6 Protection line ident signal generation circuit 7 Inversion control circuit 8 Inversion function stop circuit 11 Clock timing change circuit 21 1H delay circuit 22a First phase axis rotation circuit 22b Second phase axis rotation circuit 23 Correlation operation circuit 52 Color signal multiplexing circuit 53 RY output circuit 54 BY output circuit 100, 113 selector 101, 103, 107 1T delay circuit 104, 108, 111 Adder circuit 105, 109, 110 Subtractor circuit 112 Inverter circuit 201 Horizontal synchronization signal input terminal 202 RY component signal input terminal 203 Burst gate pulse input terminal 204 Code detection circuit 205 206 Flip-flops 207, 214 Gate 208, 210 EOR gate 209 Line ID signal output terminal 211 Up / down counter 212 Upper limiter detection circuit 213 Lower limiter detection circuit 302 Vertical synchronization signal input terminal 303 Multi-bit counter 304 Match detection circuit 305 SR flip-flop 401 Video demodulator Block 402 Video signal input terminal 403 A / D converter 404 YC separation device 405 Color signal demodulation device 406 Luminance component signal output terminal 407, 518 RY signal output terminal 408, 519 BY signal output terminal 501 Latch circuit 502 Gate circuit 503 Burst gate pulse input terminal 504, 510 LPF
505 Constant generation circuit 506 Addition circuit 507 Ramp generation circuit 508 Sine wave ROM
509 D / A converter 511 Multiplying circuit 512 4 Dividing circuit 513 4 Output terminal of FSC clock 514 Inverting circuit 515 Selector 601 Phase of burst signal of first line 602 Phase of burst signal of second line 603 A certain color signal vector is Example of input S3 Line identifier signal S402 Input video signal S405 Clock signal S404y Luminance component signal S404c Color component signal S407 RY component signal S408 BY component signal

Claims (1)

A phase-locked loop for generating a clock signal delayed 90 degrees with respect to the phase of the quantized signal clock signal synchronized with the burst signal from the color component signals are the said clock signal, the received signal is PAL system If the received signal is NTSC, the clock signal synchronized with the burst signal and the clock signal delayed by 90 degrees are selectively output based on the polarity of the RY component signal. A phase-locked loop with a clock timing changer that outputs only the clock signal
Based on the clock signal output from the phase-locked loop , the color component signal is separated into an RY component signal and a BY component signal, and the RY component signal and the BY component signal are switched at alternate timings. A color signal multiplexer for outputting the multiplexed signal,
An arithmetic unit for performing a correlation operation between the multiplexed signal obtained by rotating the phase axis by 45 degrees and the multiplexed signal obtained by delaying the horizontal synchronizing signal by one period and rotated the phase axis by 45 degrees ;
An RY inversion unit that selectively switches and outputs the polarity of the RY component signal of the signal output from the arithmetic unit based on the polarity of the RY component signal of the PAL signal;
When the received signal is a PAL system, an RY component signal output from the RY inversion unit is output, and when the received signal is an NTSC system, a multiplexed signal output from the color signal multiplexing unit An RY output unit for outputting the RY component signal of
When the received signal is the PAL system, the BY component signal of the signal output from the arithmetic unit is output . When the received signal is the NTSC system, the multiplexed signal output from the color signal multiplexing unit is output. A BY output unit that outputs a BY component signal ;
A color signal demodulating device.

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