GB2287847A

GB2287847A - Discriminating odd from even lines of a PAL video signal

Info

Publication number: GB2287847A
Application number: GB9421270A
Authority: GB
Inventors: Kyung-Seon Min; Jae-Young You; Dong-Ha Kim
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 1994-03-21
Filing date: 1994-10-21
Publication date: 1995-09-27
Anticipated expiration: 2014-10-21
Also published as: GB2287847B; DE4438974A1; KR950028934U; KR0120592Y1; GB9421270D0

Description

2287847 CIRCIAT FOR DISCRIMINATING THE LINE OF VIDEO SIGNAL

BACKGROUND OF THE INVENTION

The present invention relates to a circuit for discriminating the line of a video signal, and more particularly to a circuit for discriminating an odd line and an even line from the lines of the video signals of a PAL (Phase Alternation by Line) system.

The video signals of the PAL system have the phase difference between the lines (scanning lines), unlike the video signals of a NTSC (National Television System Committee) system. That is, two color difference signals B-Y and R-Y are modulated by a chrominance subcarrier which has the phase difference by 900 respectively during the generation of the video signal of the PAL system. The phase of the chrominance subcarrier modulating the color difference signal R-Y of the two color difference signals B-Y and R-Y is reversed by 900 in every line. Therefore, the discrimination of whether the line is the odd line or not, should be performed to correctly process the video signal of the PAL system in a video processing device. If the processing line is erroneously discriminated, it is impossible to demodulate the video signal due to the different generation of a demodulation carrier or it is also impossible to phase-correct a distorted signal.

Accordingly, the video device for processing the video signal of the PAL system has met with the needs of the accurate discrimination of the lines for the video signals of the PAL system.

In the line discrimination circuit according to the conventional art, the lines have been discriminated by using the circuit comprised of analog elements, so that there arise many problems to make the structure of circuits complicated and to reduce the confidence in the discrimination of the lines.

Further, it is difficult for the line discriminating circuit to be implemented as_ integrated circuits, thereby increasing the volume of the circuits and increasing power consumption.

i SUNEWARY OF THE INVENTION It is an object of embodiments of the present invention to provide a line discrimination circuit for correctly discriminating the lines of video signals of a PAL system, which are comprised of the digital processing circuit.

According to the present invention, there is provided a line discrimination circuit for discriminating the lines for digital video signals of a PAL system comprising:

demodulating means for demodulating two kinds of color difference signals B-Y and R-Y by eliminating a carrier from said video signal; sign detecting means for detecting the signs for a previous and current processing lines with respect to each of the two kinds of said color difference signals B-Y and R-Y demodulated during the burst interval of said video signal; and discriminating means for discriminating said current processing line from the signs of the previous and current processing lines with respect to each of the two kinds of said detected color difference signals B-Y and R- Y.

Suitably, said demodulating means comprises a multiplier for multiplying the carrier by said video signal, a first latch circuit for latching the component of said color difference signal B-Y of outputs of said multiplier, a first low pass filter for extracting said color difference signal B Y by eliminating the carrier component of two times from the component of said color difference signal B-Y latched to said first latch circuit through said low pass filter, a second latch circuit for latching the component of said color difference signal R-Y of outputs of said multiplier, and a second low pass filter for extracting said color difference signal R-Y by eliminating the carrier component from the component of said color difference signal R-Y latched to said second latch circuit through said low pass filter.

Suitably, said sign detecting means comprises a first accumulating circuit for accumulating said color difference signal B-Y in every line during the burst interval, a fifth latch circuit for latching a most significant bit indicating the sign in the sum of said accumulated color difference signal B-Y and outputting the latched most significant bit as a first sign bit, a sixth latch circuit for latching said first sign bit latched to said fifth latch circuit to every line and outputting the latched first sign bit as a second sign bit after the delay of one line, a second accumulating circuit for accumulating said color difference signal R-Y in every line during the burst interval, a seventh latch circuit for latching a most significant bit indicating the sign in the sum of said accumulated color difference signal R-Y and outputting the latched most significant bit as a third sign bit, and an eighth latch circuit for latching said third sign bit latched to said seventh latch circuit to every line and outputting the latched third sign bit as a fourth sign bit after the delay of one line.

Suitably, said discriminating means comprises an exclusive NOR gate for exclusively NORing said first and second sign bits, an exclusive OR gate for exclusively ORing said third and fourth sign bits, an AND gate for ANDing outputs of said exclusive NOR gate and said exclusive OR gate, an inverter for reversing said line discrimination signal for the previous processing line, an exclusive OR gate for exclusively ORing the outputs of said AND gate and said inverter. and a ninth latch circuit for latching the output of said exclusive OR gate to every line and outputting the latched output signal as the line discrimination signal for the current line.

Suitably, said first accumulating circuit comprises a first adder for adding said color difference signal B-Y output from said first low pass filter to the sum of said previous color difference signals B-Y and a third latch circuit for latching the output of said first adder and commonly applying the latched output signal to said first adder and said fifth latch circuit.

Suitably, said second accumulating circuit comprises a second adder for adding said color difference signal R-Y output from said second low pass filter to the sum of said previous color difference signals R-Y and a fourth latch circuit for latching the output of said second adder and commonly applying the latched output signal to said second adder and said sixth latch circuit.

A BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, advantages and features of the present invention will be more apparent from the following detailed description of an embodiment of the present invention, by way of example only, taken with the attached drawings in which:

Fig. 1 is a line discrimination circuit view according to an embodiment of the present invention; and Fig. 2 is an operational timing diagram showing the operation of the line discrimination circuit shown in Fig. 1.

DETAILED DESCRIPTION OF THE PREFERRED

EMBODIMENT Fig. 1 is a line discrimination circuit view according to the embodiment of the present invention, which comprises a demodulating circuit 44 for demodulating the two color difference signals B-Y and R-Y by eliminating the carrier from the digital video signal VIDEO of the PAL system, a sign detecting circuit 46 for detecting the signs MSBBY, MSBPBY, MSBRY and MSBPRY for the previous and current processing lines with respect to the two color difference signals B-Y and R-Y demodulated during a burst interval of the video signal, and a discriminating circuit 48 for discriminating the current processing line from the signs MSBBY, MSBPBY, MSBRY and MSBPRY for the previous and current processing lines with respect to the two color difference signals B-Y and R-Y detected from the sign detecting circuit 46.

In the construction of Fig. 1, the demodulating circuit 44 is comprised of a multiplier 2 for multiplying the video signal VIDEO by the carrier fcu, a first latch circuit 4 for latching the component B-Y' of the color difference signal B-Y among the outputs of the multiplier 2, a first low pass filter 6 (hereafter, abbreviated to "LPF") for extracting the color signal B-Y by eliminating the carrier component of two times from the component B-Y' of the color difference signal B-Y latched to the first latch circuit 4, a second latch circuit 8 for latching the component R-Y' of the color difference signal R-Y among the outputs of the multiplier 2, and a second LPF 10 for extracting the color signal R-Y by eliminating the carrier component of two times from the component R-Y' of the color difference signal R-Y latched to the second latch circuit 8.

The sign detecting circuit 46 comprises a first accumulating circuit 40 for accumulating the color difference signal B-Y in every line during the burst interval, a fifth latch circuit 16 for latching a most significant bit which indicates the sign in the sum SUMBY of the accumulated color difference signal B-Y and outputting the latched most significant bit as a first sign bit MSBBY, a sixth latch circuit 18 for latching the first sign bit MSBBY latched to the fifth latch circuit 16 to every line and outputting the latched first sign bit MSBBY as a second sign bit MSBPBY after the delay of one line, a second accumulating circuit 42 for accumulating the color difference signal RY in every line during the burst interval, a seventh latch circuit 24 for latching a most significant bit which indicates the sign in the sum SUMRY of the accumulated color difference signal R-Y and outputting the latched most significant bit as a third sign bit MSBRY, an eighth latch circuit 26 for latching the third sign bit MSBRY latched to the seventh latch circuit 24 to t every line and outputting the latched third sign bit MSBRY as a fourth sign bit MSBPRY after the delay of one line.

I The first accumulating circuit 40 comprises a first adder 12 for adding the color difference signal B-Y output from the first LPF 6 to the sum SUMBY of the color difference signals B-Y of the previous pixels and a third latch circuit 14 for latching the output of the first adder 12 and commonly applying the latched output to the first adder 12 and fifth latch circuit 16. The second accumulating circuit 42 comprises a second adder 20 for adding the 10 color difference signals R-Y output from the second LPF 10 to the sum SUMRY of the color difference signal R-Y of the previous pixels and a fourth latch circuit 22 for latching the output of the second adder 20 and commonly applying the latched output to the second adder 20 and the sixth latch circuit 24.

The discriminating circuit 48 comprises an exclusive NOR gate 28 for exclusively NORing the first and second sign bits MSBBY and MSBPBY, an exclusive OR gate 30 for exclusively ORing the third and fourth sign bits MSBRY and MSBPRY, an AND gate 32 for ANDing the outputs of the exclusive NOR gate 28 and the exclusive OR gate 30, an inverter 34 for reversing the line discrimination signal PLINE with respect to the previous line, an exclusive OR gate 34 for exclusively ORing the outputs of the AND gate 32 and the inverter 34, and a ninth latch circuit 36 for latching the output of the exclusive OR gate 34 to every line and outputting the latched output as the line discrimination signal PLINE with respect to the current processing line.

Fig. 2 is an operational timing diagram showing the line discrimination circuit shown in Fig. 1. Referring to Fig. 2, the two color difference signals B-Y and R-Y of the video signal VIDEO of the PAL system input to the line discriminating circuit shown in Fig. I are alternatively outputted as a digital signal. The color signal of the video signal VIDEO is outputted according to the lines, as referred to the following <Table I >.

<Table 1 > is Odd Line Even Line Burst Interval sin(2irft + 3/4ir) sin(21rft + 514ir) Color Signal (B-Y)sin(27rft) + (R- (B-Y)sin(2irft) - (R Interval Y)cos(2iffi) Ykos(2iffi) The video signal VIDEO, as shown in the above <Table I >, is multiplied by the demodulation carrier fcu in the multiplier 2. The two color difference signals B-Y and R-Y appear alternatively at the input video signal VIDEO, so that the demodulation carrier fcu is changed according to the two 20 color difference signals B-Y and R-Y like the following <Table 2>.

A <Table 2 >

Odd Line Even Line Burst B-Y: sin(27rft+3/47r+O), R- B-Y: sin(27rft+5/4+0), R- Interval Y: cos(27rft+3/47r+O) Y: -cos(27rft+5/4+6) Color B-Y: sin(27rft + 0), R-Y: B-Y: sin(27rft + 0), R-Y:

Signal cos(27rft + 0) -cos(27rft + 0) Interval Typically, in the video processing device of the PAL system, the chrominance subcarrier fsc is used as the modulation carrier during reproducing, on the contrary, the fcu having 40ffi is used as the demodulation carrier during recording. (The "ffi" means a horizontal scanning frequency). The result obtained by multiplying the input color signal and the modulationdemodulation carrier during the only burst interval is referred to the following < Table 3 > and < Table 4 >, separating the component B-Y' of the color difference signal B-Y and the component R-Y' of the color difference signal R-Y from the color difference signals.

Odd Line Even Line B-Y'= Asin(21ffi + 3/47r) x B-Y = Asin(2iffi + 514r) x sin(21rft + 3Mir + 0) sin(21rft + 5Mir + 0) =-A/2{cos(41rft+3/27r+O) =-A/2{cos(4rft+5/2ir+O) - COS(O)} cos(o)} <Table 4 >

Odd Line Even Line R-Y'= Asin(2rft + 3/4r) x R-Y'= Asin(2iffi + 514ir) x cos(21rft + 3/4ir + 0) cos(21rft + 5Air + 0) =-A/2{sin(4rft+3/2ir+O) =-A/2{sin(4irft+5/2ir+O) - sin(O)} sin(O)} As referred to in <Table 3>, the component B-Y' of the color difference signal B-Y is latched to the first latch circuit 4 in the rising edge of a first clock signal CLKI, and also as referred to the <Table 4>, the component R-Y' of the color difference signal R-Y is latched to the second latch circuit 8 in the falling edge thereof. Then, the carrier components of two times are eliminated by low pass filtering through the first and second LPFs 6 and 10. The first clock signal CLKI is a sampling clock for the video signal VIDEO. The color difference signal B-Y output from the first LPF 6 is t 11 expressed as the following equation (1), where the odd and even lines are the same to each other. Further, the color difference signal R-Y output from the second LPF 10 is expressed as the following equations (2) and (3) according to the lines.

B-Y = AcosO/2 (the odd and even lines) (1) R-Y = -AsinO/2 (the odd line) (2) R-Y = AsinO/2 (the even line) (3) The color difference signals B-Y and R-Y output from the first and second LPFs 6 and 10 are inputted to the first and second adders 12 and 20 of the sign detecting circuit 46.

According to the present invention, the lines of the video signals of PAL system are discriminated by using the signs of the color difference signals B-Y and R-Y of the odd and even lines output from the first and second LPFs 6 and 10 so as to detect the signs of the color difference signals 20 B-Y and R-Y in the sign detecting circuit 46.

As expressed in the above equations (1) and (2), if the odd line is itself by the discrimination of the line, the equation is formed as B-Y = AcosO/2, R-Y = -AsinO/2. Further, as expressed in the above equations (1) and (3), if the even line is itself by the discrimination of the line, the equation is formed as B-Y = AcosO/2, R-Y = AsinO/2. When the 0 is changed to have the phase difference designated, if the signs of the color difference signals B-Y and R-Y are checked, it is possible to discriminate the signs of the color difference signals B-Y and R-Y for the burst signal during accurate discrimination of the line, as referred to the following <Table 5 >.

< Table 5 >

Phase Difference When the even line is When the odd line is discriminated as itself discriminated as itself B-Y R-Y B-Y R-Y 0 < 0 < ir/2 + + + ir/2 < 0 < ir + ir < 0 < 3 ir/2 + 3r/2 < 0 < 2r + + + As expressed in the <Table 5 >, in the discrimination of the odd and even lines, if the previous and current processing lines are correctly discriminated, the sign of the color difference signal B-Y is the same in each case, on the contrary, the sign of the color difference signal R-Y is different in each case. That is, it is possible to know whether the lines are correctly discriminated or not by comparing the sign of the color difference signal R-Y.

However, if the value corresponding to the phase difference between the previous processing line and the current processing line is the same as that of the second quadrant, or if the value thereof is larger than that of the second quadrant, the lines are not correctly discriminated. For example, in the case that the phase difference 0 corresponding to the previous line is positioned at the first quadrant 0 < 0 < 7r/2 and the phase difference corresponding to the - 13 next line is positioned at the third quadrant 7r < 0 < 3 7r/2, though the two lines are correctly discriminated, it is clear that the discrimination of the lines is erroneous because the sign of the color difference signal R-Y is represented as the same sign " - ", as expressed in the above <Table 5 >. Therefore, it is possible to correctly discriminate the lines in the only case that the phase difference between the two lines is positioned within the second quadrant.

On the other hand, if the lines are erroneously discriminated, the color difference signals B-Y and R-Y during the burst interval are expressed as the 10 followings.

First, if the even line is erroneously discriminated as the odd line, the component B-Y' of the color difference signal B-Y is expressed as the following equation (4).

B-Y' = Asin(2rft + 5/41r) x sin(27rft + 3/4ir + 0) (4) Then, the color difference signal B-Y output from the first LPF 6 is expressed as the following equation (5).

B-Y = AsinO/2 (5) Further, the component R-Y' of the color difference signal R-Y is expressed as the following equation (6).

R-Y' = Asin(2.7rft + 5147r) x sin(2irft + 37r/4 + ir/2 + 0)... (6) Then, the color difference signal R-Y output from the second LPF 10 is expressed as the following equation (7).

R-Y = AcosO/2 (7) Secondly, if the odd line is erroneously discriminated as the even line,, the component B-Y' of the color difference signal B-Y is expressed as the following equation (8).

B-V = Asin(2iffi + 314r) x sin(2irft + 5Mir + 0) (8) Then, the color difference signal B-Y output from the first LPF 6 is expressed as the following equation (9).

B-Y = -Asin012 (9) The component R-Y' of the color difference signal R-Y is expressed as the following equation (10).

R-Y' = Asin(21ffi + 314ir) x {-sin(2irft + 5Mir + ir/2 + 0)}... (10) Then, the color difference signal R-Y output from the second LPF 10 is expressed as the following equation (11).

R-Y = Acos012 (11) Therefore, in the case that the 0 is changed to have the phase difference designated, if the signs of the color difference signals B-Y and R-Y are checked by using the above equations (5), (7), (9), and (11), it is possible to know the signs of the color difference signals B-Y and R-Y for the burst signal when the lines are erroneously discriminated, as referred to the following <Table 6 > <Table 6 >

Phase Difference When the even line is When the odd line is discriminated as the discriminated as the odd line even line B-Y R-Y B-Y R-Y 0 < 0 < 1r/2 + + + ir/2 < 0 < ir + ir < 0 < 3 r/2 + 3 ir/2 < 0 < 2,r + + + As expressed in the <Table 6 >, in the discrimination of the odd and even lines, if the lines are correctly discriminated, the sign of the color difference signal R-Y is the same in each case, on the contrary, the sign of the color difference signal B-Y is different in each case. That is, if the sign of the color difference signal B-Y lies in the contrary relationship between the 20 two lines, the lines are erroneously discriminated.

As mentioned above, if the value corresponding to the phase difference is the same as that of the second quadrant, or if the value thereof is larger than tnat of the second quadrant, the lines are incorrectly discriminated.

In the sign detecting circuit 46 and the discriminating circuit 48, as discussed above, it is possible to discriminate the lines by using the sum of the signs of the color difference signals B-Y and R-Y during the burst interval.

The sum of the two color difference signals B-Y and R-Y output from the first and second LPFs 6 and 10 is obtained by being accumulated by the first and second accumulating circuits 40 and 42 in every line during the burst interval. A burst flag pulse BFP input to the third and fourth latch circuits 14 and 22, as shown in Fig. 2, becomes the logic "I" during the burst interval and the outputs of the third and fourth latch circuit 14 and 22 are cleared by a reset signal RST during the rest of the intervals except the burst interval, thereby performing the accumulating operation during the only burst interval. As shown in Fig. 2, the sum SUMBY of the color difference signal B-Y is outputted by the third latch circuit 14 in the falling edge of the second clock signal CLK2 and the sum SUMRY of the color difference signal R-Y is outputted by the fourth latch circuit 22 in the rising edge thereof. The sum which is finally accumulated in every line during the burst interval is latched to the fifth latch circuit 16 and the seventh latch circuit 24 in the falling edge of the respective burst flag pulses BFP. The second clock signal CLK2 is outputted by making the first clock signal CLKI two frequency states.

The fifth latch circuit 16 latches the most significant bit indicating the sum SUMBY of the color difference signal B-Y which is accumulated and outputted as the first sign bit MSBBY and the sixth latch circuit 18 latches the Z:' A first sign bit MSBBY latched to the fifth latch circuit 16 to every line and outputs the latched first sign bit as the second sign bit after the delay of one line. Further, the seventh latch circuit 24 latches the most significant bit indicating the sum SUMRY of the color difference signal R- Y which is accumulated and outputted as the third sign bit MSBRY and the eighth latch circuit 26 latches the third sign bit MSBRY latched to the seventh latch circuit 24 to every line and outputs the latched the third sign bit as the fourth sign bit after the delay of one line.

The first to fourth sign bits MSBBY, MSBPBY, MSBRY and MSBPRY are inputted to the discrimination circuit 48, and the lines for the first to fourth sign bits are finally discriminated in the discrimination circuit 48. The line discrimination signal PLINE outputted finally from the discrimination circuit 48, is outputted as the logic " I " when the current processing line is discriminated as the even line, on the contrary, the signal is outputted as the logic "0" when the current processing line is discriminated as the odd line.

For example, if the current processing line is the even line and the previous line is the odd line, as shown in <Table 5 >, the signs of the color difference signals B-Y and R-Y are at the " + " state in the first quadrant 0 < 0 < 7r/2. Finally, the first sign bit MSBBY and the third sign bit MSBRY are all at the logic "0" state. On the other hand, since the previous line is the odd line, the sign of the color difference signal B-Y is at the " + " state and the sign of the color difference signal R-Y is at the "-" state, so that the second sign bit MSBPBY is at the logic "0" and the fourth sign bit MSBPRY is at the logic " 1 ".

The output of the exclusive NOR gate 28 is at the logic "0" and the output of the exclusive OR gate 30 is at the logic "0", thereby rendering the output of the NAND gate 32 to be at the logic "0".

Then, the line discrimination signal PLINE inputted to the inverter 34 is at the logic "0" because of indicating the previous processing line, i.e. the odd line and the output of the inverter 34 is at the logic " 1 ", so that the output of the exclusive OR gate 36 is at the logic " I ". The ninth latch circuit 38 latches the output of the OR gate 36 to the horizontal synchronizing signal 10 HSYNC and outputs the latched output as the line discrimination signal PLINE. Therefore, the line discrimination signal PLINE outputted from the ninth latch circuit 3 8 is at the logic "I", thereby indicating that the current line is the even line.

As mentioned above, it is possible to generate the carrier which is appropriate to the odd line or the even line by inputting the line discrimination signal PLINE to the modulation-demodulation carrier generating part of the video processing device of the PAL system, and it is also possible to correct the phase so as to be appropriate to the respective lines by inputting the line discrimination signal PLINE to the phase correction circuit.

Further, as mentioned above, according to the present invention, it is possible to increase the confidence in the discrimination of the lines by correctly discriminating the lines with the use of the sign of the color difference signal which appears during the burst interval of the digital video signal of the PAL system. There arise efficiencies that the volume of circuits becomes small and the current consumptions is reduced according to the integration of the digital processing circuit.

- 19 The reader's attention is directed to all papers and documents which are filed concurrently with or previous to this specification in connection with this application and which are open to public inspection with this specification, and the contents of all such papers and documents are incorporated herein by reference.

All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and/or all of the steps of any method or process so disclosed, may be combined in any combination, except combinations where at least some of such features and/or steps are mutually exclusive.

Each feature disclosed in this specification (including any accompanying claims, abstract and drawings), may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar features.

The invention is not restricted to the details of the foregoing embodiment(s). The invention extends to any novel one, or any novel combination, of the features disclosed in this specification (including any accompanying claims, abstract and drawings), or to any novel one, or any novel combination, of the steps of any method or process so disclosed.

Claims

WHAT IS CLAIMED IS:

1. A line discrimination circuit for discriminating the lines for digital video signals of a PAL system comprising:

2. A line discrimination circuit as claimed in claim 1, wherein said demodulating means comprises a multiplier for multiplying the carrier by said video signal, a first latch circuit for latching the component of said color difference signal B-Y of outputs of said multiplier, a first low pass filter for extracting said color difference signal B-Y by eliminating the carrier component of two times from the component of said color difference signal B-Y latched to said first latch circuit through said low pass filter, a second latch circuit for latching the component of said color difference signal R-Y of outputs of said multiplier, and a second low pass filter for extracting said color difference signal R-Y by eliminating the carrier component from the component of said color difference signal R-Y latched to said second latch circuit through said low pass filter.

3. A line discrimination circuit as claimed in claim I or claim 2, wherein said sign detecting means comprises a first accumulating circuit for accumulating said color difference signal B-Y in every line during the burst interval, a fifth latch circuit for latching a most significant bit indicating the sign in the sum of said accumulated color difference signal B-Y and outputting the latched most significant bit as a first sign bit, a sixth latch circuit for latching said first sign bit latched to said fifth latch circuit to every line and outputting the latched first sign bit as a second sign bit after the delay of one line, a second accumulating circuit for accumulating said color difference signal R-Y in every line during the burst interval, a seventh latch circuit for latching a most significant bit indicating the sign in the sum of said accumulated color difference signal R-Y and outputting the latched most significant bit as a third sign bit, and an eighth latch circuit for latching said third sign bit latched to said seventh latch circuit to every line and outputting the latched third sign bit as a fourth sign bit after the delay of one line.

4. A line discrimination circuit as claimed in any preceding claim, wherein said discriminating means comprises an exclusive NOR gate for exclusively NORing said first and second sign bits, an exclusive OR gate for exclusively ORing said third and fourth sign bits, an AND gate for ANDing outputs of said exclusive NOR gate and said exclusive OR gate, an inverter for reversing said line discrimination signal for the previous processing line, an exclusive OR gate for exclusively ORing the outputs of said AND gate and said inverter, and a ninth latch circuit for latching the output of said exclusive OR gate to every line and outputting the latched output signal as the line discrimination signal for the current line.

1

5. A line discrimination circuit as claimed in claim 4 as dependent upon claim 3, wherein said first accumulating circuit comprises a first adder for adding said color difference signal B-Y output from said first low pass filter to the sum of said previous color difference signals B-Y and a third latch circuit for latching the output of said first adder and commonly applying the latched output signal to said first adder and said fifth latch circuit.

6. A line discrimination circuit as claimed in claim 4 as dependent upon claim 3 or claim 5, wherein said second accumulating circuit comprises a second adder for adding said color difference signal R-Y output from said second low pass filter to the sum of said previous color difference signals R-Y and a fourth latch circuit for latching the output of said second adder and commonly applying the latched output signal to said second adder and said sixth latch circuit.

7. A line discrimination circuit as described herein with reference to and 20 as shown in the accompanying drawings.