FI885582A7 - Dubbelriktad kontrolleringssignaler givande bus-interfaceanordning foer oeverfoering av signaler mellan tvao bussystem. - Google Patents

Dubbelriktad kontrolleringssignaler givande bus-interfaceanordning foer oeverfoering av signaler mellan tvao bussystem. Download PDF

Info

Publication number
FI885582A7
FI885582A7 FI885582A FI885582A FI885582A7 FI 885582 A7 FI885582 A7 FI 885582A7 FI 885582 A FI885582 A FI 885582A FI 885582 A FI885582 A FI 885582A FI 885582 A7 FI885582 A7 FI 885582A7
Authority
FI
Finland
Prior art keywords
kontroleringssignaler
interfaceanordning
givande
dubbelriktad
bussystem
Prior art date
Application number
FI885582A
Other languages
English (en)
Finnish (fi)
Other versions
FI885582A0 (fi
Inventor
George J Barlow
Original Assignee
Honeywell Bull
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Bull filed Critical Honeywell Bull
Publication of FI885582A0 publication Critical patent/FI885582A0/fi
Publication of FI885582A7 publication Critical patent/FI885582A7/fi

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/405—Coupling between buses using bus bridges where the bridge performs a synchronising function

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Bus Control (AREA)
  • Information Transfer Systems (AREA)
  • Small-Scale Networks (AREA)
  • Logic Circuits (AREA)
  • Bidirectional Digital Transmission (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
FI885582A 1987-12-07 1988-12-01 Dubbelriktad kontrolleringssignaler givande bus-interfaceanordning foer oeverfoering av signaler mellan tvao bussystem. FI885582A7 (fi)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/129,278 US4932040A (en) 1987-12-07 1987-12-07 Bidirectional control signalling bus interface apparatus for transmitting signals between two bus systems

Publications (2)

Publication Number Publication Date
FI885582A0 FI885582A0 (fi) 1988-12-01
FI885582A7 true FI885582A7 (fi) 1989-06-08

Family

ID=22439259

Family Applications (1)

Application Number Title Priority Date Filing Date
FI885582A FI885582A7 (fi) 1987-12-07 1988-12-01 Dubbelriktad kontrolleringssignaler givande bus-interfaceanordning foer oeverfoering av signaler mellan tvao bussystem.

Country Status (13)

Country Link
US (1) US4932040A (enExample)
EP (1) EP0319663A3 (enExample)
JP (1) JPH061459B2 (enExample)
KR (1) KR920005284B1 (enExample)
CN (1) CN1017286B (enExample)
AU (1) AU602797B2 (enExample)
BR (1) BR8805602A (enExample)
CA (1) CA1322034C (enExample)
DK (1) DK681588A (enExample)
FI (1) FI885582A7 (enExample)
MX (1) MX164494B (enExample)
NO (1) NO174529B (enExample)
YU (1) YU220288A (enExample)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE68924992T2 (de) * 1988-02-23 1996-07-25 Digital Equipment Corp Symmetrische Steuerungsanordnung für Multiverarbeitung.
US5243702A (en) * 1990-10-05 1993-09-07 Bull Hn Information Systems Inc. Minimum contention processor and system bus system
US5191581A (en) * 1990-12-07 1993-03-02 Digital Equipment Corporation Method and apparatus for providing high performance interconnection between interface circuits coupled to information buses
US5341508A (en) * 1991-10-04 1994-08-23 Bull Hn Information Systems Inc. Processing unit having multiple synchronous bus for sharing access and regulating system bus access to synchronous bus
US5537655A (en) * 1992-09-28 1996-07-16 The Boeing Company Synchronized fault tolerant reset
US5644733A (en) * 1995-05-18 1997-07-01 Unisys Corporation Dual coupled partitionable networks providing arbitration logic for managed access to commonly shared busses
US5884100A (en) 1996-06-06 1999-03-16 Sun Microsystems, Inc. Low-latency, high-throughput, integrated cache coherent I/O system for a single-chip processor
US6813667B2 (en) * 2001-09-05 2004-11-02 Hewlett-Packard Development Company, L.P. Bus extender and formatter apparatus and methods
US7340553B2 (en) * 2003-03-12 2008-03-04 Nxp B.V. Data processing device and method for transferring data
GB2443867A (en) * 2006-03-21 2008-05-21 Zarlink Semiconductor Ltd Timing source with packet size controller providing a distribution of packet sizes
US8281163B2 (en) * 2010-03-16 2012-10-02 Dell Products L.P. System and method for providing power control fault masking

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CH623669A5 (enExample) * 1973-11-14 1981-06-15 Agie Ag Ind Elektronik
US4272829A (en) * 1977-12-29 1981-06-09 Ncr Corporation Reconfigurable register and logic circuitry device for selective connection to external buses
NL8202060A (nl) * 1982-05-19 1983-12-16 Philips Nv Rekenmachinesysteem met een bus voor data-, adres- en besturingssignalen, welke bevat een linkerbus en een rechterbus.
FR2531550B1 (fr) * 1982-08-06 1987-09-25 Ozil Maurice Dispositif de couplage universel pour la mise en communication d'ensembles de traitement d'informations et d'au moins une unite peripherique
US4570220A (en) * 1983-11-25 1986-02-11 Intel Corporation High speed parallel bus and data transfer method
DE3424866C2 (de) * 1984-07-06 1986-04-30 Messerschmitt-Bölkow-Blohm GmbH, 8012 Ottobrunn Verfahren und Anordnung zur Übertragung von Daten, insbesondere in einem Flugzeug
US4696019A (en) * 1984-09-19 1987-09-22 United Technologies Corporation Multi-channel clock synchronizer
GB8516609D0 (en) * 1985-07-01 1985-08-07 Bicc Plc Data network synchronisation
NL8503476A (nl) * 1985-12-18 1987-07-16 Philips Nv Bussysteem.

Also Published As

Publication number Publication date
DK681588A (da) 1989-06-08
AU2405488A (en) 1989-06-08
JPH061459B2 (ja) 1994-01-05
US4932040A (en) 1990-06-05
EP0319663A3 (en) 1991-04-10
FI885582A0 (fi) 1988-12-01
NO884762D0 (no) 1988-10-26
KR920005284B1 (ko) 1992-06-29
DK681588D0 (da) 1988-12-07
BR8805602A (pt) 1989-07-11
CN1036466A (zh) 1989-10-18
NO174529B (no) 1994-02-07
CN1017286B (zh) 1992-07-01
KR890010719A (ko) 1989-08-10
YU220288A (en) 1991-08-31
AU602797B2 (en) 1990-10-25
NO884762L (no) 1989-06-08
EP0319663A2 (en) 1989-06-14
NO174529C (enExample) 1994-05-18
MX164494B (es) 1992-08-20
CA1322034C (en) 1993-09-07
JPH01191249A (ja) 1989-08-01

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Legal Events

Date Code Title Description
FD Application lapsed
FD Application lapsed

Owner name: HONEYWELL BULL INC.