FI831513L - Apparat foer direkt fraon minne till minne skeende kommunikation mellan datorer - Google Patents

Apparat foer direkt fraon minne till minne skeende kommunikation mellan datorer

Info

Publication number
FI831513L
FI831513L FI831513A FI831513A FI831513L FI 831513 L FI831513 L FI 831513L FI 831513 A FI831513 A FI 831513A FI 831513 A FI831513 A FI 831513A FI 831513 L FI831513 L FI 831513L
Authority
FI
Finland
Prior art keywords
minne
skeende
datorer
fraon
mellan
Prior art date
Application number
FI831513A
Other languages
English (en)
Finnish (fi)
Other versions
FI831513A0 (fi
Inventor
William D Strecker
Robert E Stewart
Samuel Fuller
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Publication of FI831513A0 publication Critical patent/FI831513A0/fi
Publication of FI831513L publication Critical patent/FI831513L/fi

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/167—Interprocessor communication using a common memory, e.g. mailbox
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/177—Initialisation or configuration control

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Small-Scale Networks (AREA)
  • Multi Processors (AREA)
  • Communication Control (AREA)
  • Computer And Data Communications (AREA)
FI831513A 1982-05-07 1983-05-03 Apparat foer direkt fraon minne till minne skeende kommunikation mellan datorer FI831513L (fi)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US37598482A 1982-05-07 1982-05-07

Publications (2)

Publication Number Publication Date
FI831513A0 FI831513A0 (fi) 1983-05-03
FI831513L true FI831513L (fi) 1983-11-08

Family

ID=23483204

Family Applications (1)

Application Number Title Priority Date Filing Date
FI831513A FI831513L (fi) 1982-05-07 1983-05-03 Apparat foer direkt fraon minne till minne skeende kommunikation mellan datorer

Country Status (6)

Country Link
EP (1) EP0094177B1 (fr)
JP (1) JPS5940744A (fr)
AU (1) AU568490B2 (fr)
CA (1) CA1189195A (fr)
DE (1) DE3380191D1 (fr)
FI (1) FI831513L (fr)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CH667543A5 (en) * 1985-04-19 1988-10-14 Bbc Brown Boveri & Cie Data communication for processing network - using stored table in communication unit for each node defining data segment storage location
IN168469B (fr) * 1986-02-24 1991-04-06 Ibm
EP0296862B1 (fr) * 1987-06-24 1995-05-10 Westinghouse Electric Corporation Transfert d'informations entre processeurs
US5179665A (en) * 1987-06-24 1993-01-12 Westinghouse Electric Corp. Microprocessor information exchange with updating of messages by asynchronous processors using assigned and/or available buffers in dual port memory
EP0335812B1 (fr) * 1988-03-28 1995-05-10 International Business Machines Corporation Système d'initialisation pour processeur secondaire
FR2662522B1 (fr) * 1990-05-28 1994-08-12 Copernique Dispositif informatique de transfert de donnees en mode rafale.
EP0459877A1 (fr) * 1990-05-28 1991-12-04 Copernique, Societe Anonyme Dispositif informatique de transfert de données en mode rafale
DE69129841T2 (de) * 1990-09-28 1998-12-03 Fujitsu Ltd Nachrichtensteuerungssystem in einem datenkommunikationssystem
JP3251147B2 (ja) * 1995-04-14 2002-01-28 日本電気株式会社 プロセッサ間データ転送方法およびその装置
DE69834253T2 (de) 1998-10-21 2007-02-01 Alcatel System und Verfahren zur Ausführung eines bestimmten Befehls zwischen erstem und zweitem Endgerät
JP2009301101A (ja) * 2008-06-10 2009-12-24 Nec Corp プロセッサ間通信システム、プロセッサ、プロセッサ間通信方法、および、通信方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5631253A (en) * 1979-08-23 1981-03-30 Hitachi Ltd Transmission control system
JPS5833972B2 (ja) * 1979-11-12 1983-07-23 富士通株式会社 計算機システム間通信方式
US4560985B1 (en) * 1982-05-07 1994-04-12 Digital Equipment Corp Dual-count, round-robin ditributed arbitration technique for serial buses

Also Published As

Publication number Publication date
EP0094177B1 (fr) 1989-07-12
JPS5940744A (ja) 1984-03-06
EP0094177A2 (fr) 1983-11-16
FI831513A0 (fi) 1983-05-03
EP0094177A3 (en) 1985-01-09
CA1189195A (fr) 1985-06-18
AU568490B2 (en) 1988-01-07
AU1350083A (en) 1984-11-08
DE3380191D1 (en) 1989-08-17
JPH0320094B2 (fr) 1991-03-18

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Legal Events

Date Code Title Description
FD Application lapsed

Owner name: DIGITAL EQUIPMENT CORPORATION