FI75705C - KOPPLINGSANORDNING FOER AOSTADKOMMANDE AV FASSAMSTAEMMIGHET MELLAN TAKTPULSER OCH SYNKRONISERINGSBITAR HOS DATAGRUPPER. - Google Patents

Description

1 75705

Switching device for generating a phase balance between the synchronous pulses and the synchronizing bits of the data groups

The invention relates to a circuit for providing and maintaining synchronization between group synchronization pulses derived from locally generated bit synchronization pulses and groups of binary coded signals at regular predetermined bit locations in synchronization devices and, in particular, in data transmission devices.

Switching for monitoring telegraph transmission paths in order to prevent a certain relative transmission error of telecommunication transmission centers, in particular telegraph centers, is already known (DE-1 264 491), whereby a certain number of compares such that they limit the allowable distortion range by setting the allowable distortion determining device when the ratio of the specified number of non-distorted remote printer characters to the specified number of simultaneously transmitted remote printer characters is less than the specified transmission errors. However, it is not known from this connection to achieve and maintain synchronization between the group synchronization pulses derived from the locally generated bit synchronization pulses and the polarity strings preceding the synchronization bits at regular predetermined bit positions in the groups of binary coded signals.

Furthermore, a circuit is known for monitoring synchronization in data transmission devices (DE-1 291 767), in which the received and locally generated synchronization signals are in each case fed to the input of an AND gate, the output of which is connected to the first 2 75705 data memory 1 counter input and the second input memory to return this to a predetermined calculation step. In this case, the locally generated synchronization signals are passed on to the counter of the second data memory counter. However, this known connection is obviously not suitable for achieving and maintaining synchronization between the group synchronization pulses derived from the locally generated bit synchronization pulses and the polarity strings preceding the synchronization bits at regular predetermined bit positions in the groups of binary coded signals.

There are also known methods and devices for monitoring the synchronization between a data transmitter and a data receiver in digital data transmission devices, in particular remote recording devices (DE-1 815 233), in which data are transmitted in the form of individual data sections of equal length and synchronization between them. the data is compared to the existence of the synchronizing words and the matches between them and the test words on the receiving side 1a are compared. In this case, the data to be transmitted are combined in a manner known per se on the transmission side 1a from the number of bits preceding the individual data words and the synchronization words connected between them in a certain order. The received data is examined on the receiving side 1a at specified times to determine the synchronization words, and the consistency between them and the current test word is compared within a predetermined minimum number of bit positions. The occurrence of more uniformities than non-conformances within a predetermined number of comparisons is considered sufficient synchronization. In this case, however, it may be possible to end up with sufficient synchronization when the first correctly received synchronization word is detected for the first time. In this case, however, it is detrimental that this mode of operation is of course not useful for achieving and maintaining synchronization between groups of synchronous bits pulsed from locally generated bit sync pulses and a binary coded 3,75705 signal.

Finally, there is also known a connection for providing and monitoring verbatim synchronization between receiver partition pulses and incoming data in remote printers and similar data transmission devices (DE-2 147 565), for which the code-like transmission of structures preceding synchronously transmitted codewords is continuously tested. and by means of a coded tester connected thereto, which gives a signal indicating the existence of a complete codeword and thus a synchronization, the information currently in the shift register and the expected information being consistent with respect to the structure preceding the codewords. In this case, the counter synchronized in the rhythm of the code elements also gives, after a number of counting pulses from the input side corresponding to the number of elements of the complete code message code, a test to the pre-switched gate circuit made when the test signal is present only when a signal indicating the existence of a complete codeword in the shift register is present at the same time, it allows the longest 1 counting pulse to be applied to the counter. Although with this known switching arrangement it is possible to produce a telemark synchronization device which allows the implementation and monitoring of literal synchronization between the partition pulses of the data receiver and the incoming data, this known switching arrangement is certainly not suitable for group-synchronized group to achieve and maintain synchronization of the synchronization bits at a particular bit location.

4 75705 ______

The invention is thus based on the object of demonstrating the means by which, in connection with said type of switching in the preamble, it is relatively easy to obtain and maintain synchronization between group synchronization pulses derived from locally generated bit synchronization pulses and binary coded signal groups of regularly predetermined bit positions.

The above object is achieved by the features given in the characterizing part of claim 1.

The invention has the advantage that, at a relatively low switching technical cost, the desired synchronization between the group synchronization pulses derived from the locally generated bit synchronization pulses and the synchronization bits present in the groups of the binary coded signal can be achieved and maintained. In this case, it is possible to cope with relatively few highly integrated components, both to find the so-called group rate and also to achieve a phase balance between the bit-synchronization pulses and the synchronization bits of the data groups.

In order to produce reference signals with a small technical input, it is expedient to use the features mentioned in the characterizing part of claim 2.

Only for further derivation of data sets that are synchronous with the pace of the pulses, it is expedient to use the object mentioned in the 3rd characteristic of the patent claim.

In order to detect and indicate the possible absence of synchronous pulses, it is expedient to use the features mentioned in the characterizing part of claim 4.

In order to prevent the loss of group synchronization in beam interference, it is expedient to use the features set forth in the characterizing part of claim 5.

5 75705

Exemplary embodiments of the invention will now be described with reference to Figures 1-7, in which: Figure 1 shows a schematic circuit diagram of a switching device for generating a phase synchronous phase between synchronous pulses and data group synchronization bits; shows a switching device for phase synchronization, from which device only synchronous data groups are passed on to the following switching devices, Fig. 4 shows a switching device for generating a phase synchronizer, which device further transmits data signals to the following switching devices only in the Fig. 6 shows a switching device for synchronizing several data signals with a single period of synchronous pulses, Fig. 7 shows a switching device for synchronizing several data signals with a single period of synchronous pulses whose pulse repetition frequency is a multiple of the fundamental frequency.

Figure 1 shows a switching device for generating a phase balance between the clock pulses and the synchronization bits of the data groups. For example, according to Fig. 2, it is a question of the clock pulses T10 and the synchronization bits S1, S2 of the groups EN1, EN2, which are transmitted within the data signal D10. The groups each contain ten bits. The first bit d10 of the group EN1 is a status bit, the second bit is the synchronization bit S1 and then follows the other eight bits dl3-dl9, which are considered as actual payload bits. The data signal D10 is input to the switching device shown in Fig. 1, and after generating the phase equalizer, the data signal shown below in Fig. 2 is transmitted between the synchronous pulses T10 and the data group synchronization bits. The switching device shown in Fig. 1 can be arranged on the receiving side of the data transmission system, whereby the synchronous pulses then correspond to the reception rate of the system in terms of frequency and phase level. The transfer method itself is then indifferent. The data signal D11 'can be further routed to other transmission devices, for example data terminals and transmission centers.

Fig. 1 shows a bottom view of the synchronous sensor TG100, which produces the synchronous signal T100 shown in Fig. 2. The individual pulses of this clock signal correspond in each case to the individual bits of the data signal D10. The frequency divider FT1 causes a frequency division with respect to l and outputs a synchronous signal T10 via its output. The divisor n corresponds to the number of bits grouped together, and since in this embodiment, the groups EN1, EN2 each consist of ten bits, n = 10.

As can be seen in Figure 1, the data signal D10 is input in series to the shift register SR, and the individual bits of the data signal are further transmitted in step with the clock signal T100. The pulses of the clock signal T100 thus act as transfer pulses. The shift register SR contains at least n memory elements, the outputs of which can be connected individually via a switch SW to the input of the memory SP1. Depending on the SW position of this switch, the data signal D10 is decelerated in a controllable manner.

The memories SP1, SP2 each store one bit. For example, bistable tilt levels can be arranged as memories SP1, SP2. The memory SP1 receives the bits to be stored via the switch SW. Memory SP2 receives the bits to be stored via the output of memory SP1. These bits are stored during the positive edge of the clock signal T10. For example, at time tl3, bit dl3 is stored in memory SP1 and bit d3 is stored in memory SP2 (10 bits before bit dl3).

Bits dl3, d3 remain stored up to time t23 1 75705 there. As already mentioned above, the distance between the individual edges of the synchronous signal T10 is 10 synchronous periods T100, in which n bits are generally received.

The ABSOLUTE-OR element EX compares the bits stored in the memories SP1 and SP2 with each other. For example, at time tl4, bits d3 and dl3 are compared with each other, and at time t24, bits dl3 and d23 are compared with each other. Element EX only outputs a 1 signal when both inputs have different binary values. Since the binary values of the synchronization bits usually vary from group to group, there could be a question of synchronization bits for both bits d3 and dl3 only when a 1 signal is passed through the output of the element EX. If a 0 signal is passed through the output of the element, then there can be no question of synchronization bits of successive groups for both bits d3 and dl3. However, the 1-signal at the output of the element EX does not necessarily give an indication of the two synchronization bits of the successive groups, because, for example, the binary values d3 and dl3 could also be randomly different as data bits. For this reason, interpretation is appropriately made through several groups.

The output of the element EX is connected on the one hand via the inverter INI to the AND element UI and on the other hand directly to the AND element U2. The second inputs of these two AND members U1 and U2 receive pulses T11 produced by the differentiation stage DIFF. The pulses T11 are formed by the rear ramp of the pulses T10. The reference pulses VI are transmitted via the output of the AND element UI, which indicate an erroneous synchronization, because in these cases 0 signals are output from the output of the element EX in each case. For example, according to Figure 2, it is assumed that the binary values d3 and d13 on the one hand and the binary values d23 and d33 on the other hand are similar. In this way, reference pulses V1 are formed at times t1 and t34, respectively. In contrast, a reference pulse V2 is transmitted via the output of the element U2 8 75705, which gives an indication of either successive synchronization pulses or randomly different binary values of the data signal D10. For example, both binary values <313 and d23 must be assumed to be randomly different because this is not a case of synchronization pulses of successive groups.

The reference pulses VI are fed to the counter Z1 as count pulses. The pointers Z1 of this counter thus increase to a predetermined maximum point; then the country indicated by the counter is automatically returned to the start address. Upon reaching a predetermined maximum indication, the counter Z1 transmits an error pulse F to the counter Z2. According to Fig. 2, it was assumed, for example, that at time t34, the counter Z1 reaches its maximum indicated and transmits an error pulse F. For example, such an error pulse F can be transmitted whenever the counter Z1 reaches the maximum indicated four.

The counter Z2 calculates the error pulses F and increments its indication until it has reached a predetermined indication. The counter Z2 is then automatically reset to its output indication, e.g. For example, the maximum counter indicator can be set to ten. For each indication of the counter Z2, the position of the switch SW is arranged. The maximum indication of the counter Z2 is equal to the number n of the elements of the transfer register SR and equal to the number of different positions of the switch SW. The positions indicated by switch Z2 control the positions of switch SW. Thus, when the indication of the counter Z2 changes, the next position of the switch SW is adjusted, which thus switches through the output of the next element of the shift register.

To explain the operation of the switching device shown in Fig. 1, it is assumed that the groups of the data signal D10 shown in Fig. 2 assume a random phase position with respect to the clock pulses T10. It is further assumed that on the basis of the data signal D10 it is certainly not possible to detect 9 75705 where the individual groups begin and end. With the switching device shown in Fig. 1, on the one hand, a group rhythm is found in one operating phase and, on the other hand, a defined phase position of the data signal with respect to the synchronous pulses T10 is produced. For example, it is assumed that the defined phase position of the data signal is reached when the center portions of the synchronization bits coincide with the leading edges of the synchronous pulses T10. In principle, however, it could also be thought that the synchronization bits are phase-chained in a defined different way with the clock pulses T10.

With the help of Figures 1 and 2, it has already been explained that at time t34 the error pulse F is transmitted to the counter Z2. The switch position indicated by the counter Z2 and the switch SW is changed in this way. In the changed switch position, the bits of the data signal D11 appear either one bit more or less decelerated depending on the direction in which the switch position of the switch SW was changed. Assuming that the switch position of the switch SW is changed clockwise by the increase indicated by the counter Z1, then the data signal D11 is decelerated by one bit more in the new switch position than above. In this way, the bits of the data signal D10 which have been shifted stepwise by one bit with respect to the clock pulses T10 are stored in the memories SP1 and SP2. When the reference pulses VI are transmitted again under these conditions, then an error pulse F is also generated again, which changes the indicator indicated by the counter Z2 and which causes a change in the switch position of the switch SW. The switch positions are changed until no reference pulses V1 are produced and the group rhythm is reached. This state is reached at a time which can no longer be represented by the time scale of Figure 2. When the time scale is not taken into account, the data signal D11 ', which has a defined phase position with respect to the clock pulses T10, is finally adjusted. In this phase position, only the synchronization bits whose binary values change according to the condition are taken into both memories SP1 and SP2, so that the element EX continuously outputs 1 values. The inverter blade INI then prevents the production of other reference pulses V1 ___- I _____ 10 75705, so that no error pulse F is produced and the indication of the counter Z2 is no longer changed. When the indicator indicated by the counter remains the same, the same switch position of the switch SW also remains adjusted and the defined phase position of the data signal D11 'is produced.

In a slightly more general representation, the shells contain one synchronization bit at a time and a total of n bits at a time. Within the data signal D10, the groups are fed in series to the shift register SR and output via the switch SW as a slow-motion data signal D11. The slowed down data signal D11 is fed to a reference device consisting of both memories SP1, SP2, elements EX, UI, U2, inverters INI and a degree of differentiation DIFF. This comparator compares the bits of the data signal D11 transmitted via the switch SSW with the bits previously transmitted n bits in each case and outputs one of the two reference pulses VI or resp. V2, which signal an incorrect synchronization or, possibly, a found synchronization. The first counter Z1 counts the reference pulses VI for erroneous synchronization, and upon reaching the predetermined assigned counter Z1 outputs the error signal F1 to the second counter Z2. Each error signal F changes the position indicated by the counter Z2 and correspondingly also the position of the switch SW until the group sync no longer produces any error signals F.

Figure 3 shows a switching device for generating a phase equalizer from a device from which only synchronous groups are passed on. As shown in Fig. 2, the groups EN1, EN2 of the data signal D11 have not yet been phased with respect to the clock pulses T10. In the phased state, the element EX continuously transmits 1 signals, so that the reference pulses V2 increase the value indicated by the counter Z3. Before reaching the predetermined counter assignment, the counter Z23 outputs a signal A = 0, the memory SP3 of which still leads as a sleep state A '= 0. This signal acts as an alarm and informs the following switching devices that the criteria of the phased state 11 75705 have not yet been met. For the duration of the signal A '= 0, the AND member U3 remains closed so that the data signal D11 is not passed on. After reaching the counter assignment, the counter Z3 outputs the signal A = 1. The memory SP3 receives this signal, as a result of which A '= 1 and the gate U3 are opened. A phased data signal D12 is now output via the output of this gate. The other pulses V2 cause the level change of the signal A to A = 0 without affecting A '= 1.

The switching device shown in Fig. 4 is a further development of the switching devices described so far, which indicates the possible omission of the synchronous pulses T10.

It further includes a re-triggerable monostable tilt stage with a setting input T10, an OR member 01 and an inverter IN2.

The time constant of this tilting stage is selected so that the smooth uninterrupted period of the synchronous pulses T10 at the tilting stage output results in a continuous signal 1. This signal is fed to the third input of the gate U3 and through the inverter IN2 and the OR member 01 to the memory SP3 as a release signal.

If clock T10 is omitted, then the release signal is lost. Gate U3 is closed and memory SP3 is restored. This means that the data signal D11 is not further derived and an alarm is signaled to the following components by means of A '= 0.

In order to prevent the reference pulses VI formed by the interference bursts from causing a new phase in the phased state, a blocking time can be started via the switching device shown in Fig. 5, during which the reference pulses VI do not increase the counter Z1 so that no error pulse F can occur. Only after the inhibit time can an error pulse F occur in connection with the other reference pulses VI. Thus, an attempt is made again to _____ J- u 75705 to phase the data signal.

Fig. 5 further shows a memory SP4, gates U4, IN3 and IN4 and a time element ZG as a switching block. The time element has a count input with synchronous pulses T10 for generating a blocking time, a reset input r which is activated when a signal VI occurs in the synchronous state, and two outputs which produce reset signals for the counter Z1 and the memory SP4.

The counter Z3 produces a signal A representing a non-synchronous state with A = 0 and a synchronous state with A = 1. In non-synchronous mode, A = 0 or resp. A '= 0 holds the time element via ZG U4 and IN4, even when pulses VI occur, in the state restored due to the 0 signal from the memory SP4. The return wires to counter Z1 and memory SP4 are not active.

If the synchronous phase is reached, then signal A = 1 is taken to memories SP3 and SP4. Memory SP3 indicates the phased state for the following devices using SP '= 1ίη. The memory SP4 keeps the counter Z3 at its highest point due to the lock in the UA member U2 and allows the signal VI to activate the time element. The time element is such that the disappearance of the signal VI cannot again stop the blocking time started once. Only after this has ended can the reset signal start working again in the time element.

If the pulse VI has activated the time element during the synchronous phase, then the counter signal Z1 is held in its basic position by the reset signal during the blocking time, so that even when signals VI occur in large numbers, as in the case of disturbances, no error signal F is produced. .

At the end of the blocking time, counter Z1 is released again due to the omission of the reset signal. At the same time, 13 75705 with the second recovery signal puts the memory SP4 to its dormant state.

This causes the counter Z3 to be released via IN3 and the time element itself to be reset.

With the next signal V2, the counter Z3 outputs the signal A = 0, while maintaining A '= 1. Only when an error signal F occurs due to several signals VI, the memory SP3 is reset and A '= 0 is handed over. This means the same as a new phase.

However, if no more signals VI occur, then the counter Z3 reaches the highest indicated and releases A = 1 again. The memory SP4 receives this signal A = 1 and allows the time element to be started when a pulse VI occurs. In this second case, the signal A '= 1 was retained,

Figures 1-5 have so far explained the phasing of a single data signal D10. In most practical cases, several data signals have to be phased. For example, in addition to the data signal D10 shown in Fig. 2, there may be another data signal D20 according to Fig. 6 having the same structure as the data signal D10, but a different phase station. In this case, the groups of both data signals D10 and D20 must be matched in phase with the synchronous pulses T10. The synchronous signal T10 is phased by the synchronization switching device SYI and the data signal D20 is phased by the synchronization switching device SYII. As synchronization switching devices, SYI or resp. SYII can be used with one of the switching devices SV1, SY2, SY3, SY4 shown in Figs. 1, 3, 4, 5.

By selecting the appropriate technology, the key components of the synchronization connections SYI and SYII can be implemented with a single component. This can be a special application- _ τ ____ 14 75705 component. However, due to a special strategy (Anwenderbaustein) for finding the synchronization bit in the controlled transfer register, it is also possible to form a switching device with a microcomputer. Depending on which of these switching devices is used, different output signals are generated, which in Fig. 6 are generally denoted by reference numerals DI or resp. DII.

Figure 7 relates to the case of several data signals DIO, D30 with different bit rates. The data signal D30 thus differs from the data signal D10 shown in Fig. 2 due to the number of bits transmitted per second.

However, it is assumed that the groups of these data signals D10 and D30 in each case consist of n bits and that there is a common basic period determined by the clock pulses T1. The synchronous pulses T10 are produced, as explained by Fig. 1, by means of the synchronous sensor TG100 and the frequency divider FT1.

The same applies to the beats for the data signal D30. If we look at the use of a synchronization device in practice, then it is found that the search for synchronization bits is necessary, firstly, in the case of commissioning and, secondly, in the event of disturbances on the data lines. The comparison and interpreter connections VBS1, VBS2, VBS3, VBS4 of the synchronization devices are thus loaded in time mainly by synchronism monitoring.

However, it is not necessary to monitor the phased data signal continuously. It is sufficient that the synchronicity be checked from time to time. Now that it is still assumed that two data lines are rarely used at the same time, it makes sense to establish the reference and interpreter connections VBS1, VBS2, VBS3, VBS4 for both data signals D10 and D30 only once and to provide the switching circuit U5. This switching leads the VBS to the data and data of the data signal and passes the control signals on to the corresponding devices of the synchronization device.

is 75705 As a result of this measure, the input also becomes favorable for the processing of several data signals. This switching device can also be implemented in a microcomputer, which can likewise perform switching.

Claims (5)

1. Coupling in groups of synchronous bits at a predetermined bit position of a predetermined bit position in a group of group synchronization pulses derived from locally generated bit synchronization pulses and a binary coded signal in order to achieve and maintain synchronization in the signal transmission devices, in particular in telecommunication devices, in particular sampling controlled shift register (SR) with a number of shift register stages (1 to 10) <n = 10> at least equal to the total number of status bits (d10), synchronization bits (dll) contained in the group of signals (D10) (e.g. EN1) ) and the number of data bits, or data bits (dl2 to dl9) (ten), which receive the bits in serial form in its memory, in batch the binary coded signal input in series (D10) and provide it in step with the locally generated bit sync signal (T100) further shifted from its shift register (1 to 10) to the parallel reference outputs in parallel, and that the post-switched comparator (VGL) compares the time from the individual shift register stage (e.g. in distance group synchronization (T10), the number of bit synchronization pulses (T100) delayed by a number (e.g., d23) of bits (e.g., d23) corresponding to the number (three) of the above shift register stages (1-3) (b13> EX) n) and provides a signal indicating the existence of synchronization (V2> the binary values (L and H or H and L) of these bits (d20 and d10 - d29 and dl9) and the expected synchronization bits (d21 = S2) for two successive groups in each case, e.g. and dll = SI) of the binary values (L and H) at least a rough match (EX provides 1 signal) two successive groups (for example, 17 75705 EN2 and END of the binary values <L and H or H and L of these bits Cd20 and d10 to d29 and d19>) and the expected synchronization bits (d2i = S2 and dll * SD at least a rough mismatch of the binary values <EX provides an O signal) with a predetermined number (four), the switching device <SW> so often changes the output direction of the next next shift register stage (e.g. 5) via VI over Z1 Z2) until the reference device (V6L) recognizes the binary values (L and H or H and L) of these bits (d20 and d10 to d29 and d19) and the expected synchronization bits (d21 = S2 and dll = at least a rough match of the SD binary values (L and H) (EX gives a 1 signal) and provides a signal indicating the existence of synchronization (V2). Switching according to Claim 1, characterized in that the reference device (VGL) essentially comprises a first memory (SPD, a second memory (SP2) and a logic unit (EX), and that the delayed data signal (D11) transmitted via the switching device (SW) is derived from the first memory (D11). SPD input and its output signal to the second memory (SP2) that only those bits that occur simultaneously with group synchronization (T10) are transferred to each memory (SP1, SP2), that the outputs of the first and second memories (SP1, SP2) are connected to the logic unit (EX ) inputs, and that the logic unit (EX) provides reference pulses (VI) in the case of missing synchronization or a signal indicating the existence of synchronization (V2), respectively. A circuit according to claim 2, characterized in that it has a counter (Z3) which counts the signals (V2) indicating the existence of synchronization and which transmits a mild alarm signal (T "---- ιβ 75705 before reaching a predetermined special calculation situation (--- A = 0) and after reaching this calculation situation to the first gate (U3) of the pass signal (A = 1), through which the delayed data signal (D11 ') is passed on (Fig. 3). Switching according to one of Claims 1 to 3, characterized in that the group synchronization (T10) controls a monostable flip-flop <MF> which is connected to a gate <U3> serving the transmission of data signals and produces a return signal memory <SP3> via an inverter (IN2). which can be controlled via the presence of a synchronization signal <V2 or vast A). Switching according to one of Claims 2 to 4, characterized in that a special memory (SP4) is used to set a predetermined waiting time during which the counter (Z1) counting down the reference pulses (VI) is stopped for missing synchronization.