FI7354U1 - JTAG testing arrangement for an integrated circuit - Google Patents

JTAG testing arrangement for an integrated circuit

Info

Publication number
FI7354U1
FI7354U1 FI20050328U FIU20050328U FI7354U1 FI 7354 U1 FI7354 U1 FI 7354U1 FI 20050328 U FI20050328 U FI 20050328U FI U20050328 U FIU20050328 U FI U20050328U FI 7354 U1 FI7354 U1 FI 7354U1
Authority
FI
Finland
Prior art keywords
integrated circuit
testing arrangement
jtag testing
jtag
arrangement
Prior art date
Application number
FI20050328U
Other languages
Finnish (fi)
Swedish (sv)
Inventor
Mikko Simonen
Ilkka Reis
Original Assignee
Patria Systems Oy
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Patria Systems Oy filed Critical Patria Systems Oy
Priority to FI20050328U priority Critical patent/FI7354U1/en
Publication of FIU20050328U0 publication Critical patent/FIU20050328U0/en
Priority to PCT/FI2006/050438 priority patent/WO2007042622A1/en
Application granted granted Critical
Publication of FI7354U1 publication Critical patent/FI7354U1/en

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318516—Test of programmable logic devices [PLDs]
    • G01R31/318519—Test of field programmable gate arrays [FPGA]
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318558—Addressing or selecting of subparts of the device under test
FI20050328U 2005-10-12 2005-10-12 JTAG testing arrangement for an integrated circuit FI7354U1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FI20050328U FI7354U1 (en) 2005-10-12 2005-10-12 JTAG testing arrangement for an integrated circuit
PCT/FI2006/050438 WO2007042622A1 (en) 2005-10-12 2006-10-12 A jtag testing arrangement for an integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FI20050328U FI7354U1 (en) 2005-10-12 2005-10-12 JTAG testing arrangement for an integrated circuit

Publications (2)

Publication Number Publication Date
FIU20050328U0 FIU20050328U0 (en) 2005-10-12
FI7354U1 true FI7354U1 (en) 2007-01-12

Family

ID=35185302

Family Applications (1)

Application Number Title Priority Date Filing Date
FI20050328U FI7354U1 (en) 2005-10-12 2005-10-12 JTAG testing arrangement for an integrated circuit

Country Status (2)

Country Link
FI (1) FI7354U1 (en)
WO (1) WO2007042622A1 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2331979B1 (en) * 2008-09-26 2012-07-04 Nxp B.V. Method for testing a partially assembled multi-die device, integrated circuit die and multi-die device
CN102404167B (en) * 2011-11-03 2014-02-19 清华大学 Protocol test generating method of parallel expansion finite-state machine based on variable dependence
CN102707919A (en) * 2012-05-28 2012-10-03 上海海事大学 Device and method for controlling FIFO (First In First Out) read-write by using finite state machine (FSM)

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6191603B1 (en) * 1999-01-08 2001-02-20 Agilent Technologies Inc. Modular embedded test system for use in integrated circuits
JP2004500712A (en) * 2000-01-18 2004-01-08 ケイデンス・デザイン・システムズ・インコーポレーテッド Hierarchical test circuit structure for chip with many circuit blocks
US7080789B2 (en) * 2003-05-09 2006-07-25 Stmicroelectronics, Inc. Smart card including a JTAG test controller and related methods

Also Published As

Publication number Publication date
FIU20050328U0 (en) 2005-10-12
WO2007042622A1 (en) 2007-04-19

Similar Documents

Publication Publication Date Title
DE602006016445D1 (en) TEST BASE FOR INTEGRATED CIRCUITS
DE602006002141D1 (en) Airbag for an airbag
DE502006000019D1 (en) Integrated circuit
DK1946047T3 (en) DEVICE FOR INTERFEROMETRICAL MEASUREMENT
GB0514921D0 (en) An inspection device
DE602007013340D1 (en) Device module for an air circuit breaker
DE602006019676D1 (en) Detection circuit for magnetic field detector
GB0514920D0 (en) An inspection device
NO20050592A (en) Device for flow measurement
DE602007006702D1 (en) Power protection circuit for an integrated circuit
DE602006002691D1 (en) Holding device for an airbag module
DE602006011224D1 (en) Electronic device
FI20045312A (en) Testing procedure for electronic devices
DE602006002880D1 (en) Fast P-Domino register circuit
HK1142682A1 (en) Integrated circuit probe card analyzer
FI7354U1 (en) JTAG testing arrangement for an integrated circuit
DK1795984T3 (en) Functionality Test Procedure
DE602006014927D1 (en) Tester
DE602006009321D1 (en) Securing the test mode of an integrated circuit
FI20051228A0 (en) Component housing comprising an integrated circuit
DE602006004811D1 (en) Tester
DE602005011967D1 (en) JTAG port
DE112007001583A5 (en) Circuit carrier device
DE502005011235D1 (en) TEST BENCH
DE602005013828D1 (en) OUTER MATERIAL FOR ELECTRONIC DEVICE

Legal Events

Date Code Title Description
PC Transfer of assignment of patent

Owner name: PATRIA SYSTEMS OY

Free format text: PATRIA SYSTEMS OY

FGU Utility model registered

Ref document number: 7354

Country of ref document: FI