FI7354U1 - Integroidun piirin JTAG-testausjärjestely - Google Patents

Integroidun piirin JTAG-testausjärjestely

Info

Publication number
FI7354U1
FI7354U1 FI20050328U FIU20050328U FI7354U1 FI 7354 U1 FI7354 U1 FI 7354U1 FI 20050328 U FI20050328 U FI 20050328U FI U20050328 U FIU20050328 U FI U20050328U FI 7354 U1 FI7354 U1 FI 7354U1
Authority
FI
Finland
Prior art keywords
integrated circuit
testing arrangement
jtag testing
jtag
arrangement
Prior art date
Application number
FI20050328U
Other languages
English (en)
Swedish (sv)
Inventor
Mikko Simonen
Ilkka Reis
Original Assignee
Patria Systems Oy
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Patria Systems Oy filed Critical Patria Systems Oy
Priority to FI20050328U priority Critical patent/FI7354U1/fi
Publication of FIU20050328U0 publication Critical patent/FIU20050328U0/fi
Priority to PCT/FI2006/050438 priority patent/WO2007042622A1/en
Application granted granted Critical
Publication of FI7354U1 publication Critical patent/FI7354U1/fi

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318516—Test of programmable logic devices [PLDs]
    • G01R31/318519—Test of field programmable gate arrays [FPGA]
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318558—Addressing or selecting of subparts of the device under test

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
FI20050328U 2005-10-12 2005-10-12 Integroidun piirin JTAG-testausjärjestely FI7354U1 (fi)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FI20050328U FI7354U1 (fi) 2005-10-12 2005-10-12 Integroidun piirin JTAG-testausjärjestely
PCT/FI2006/050438 WO2007042622A1 (en) 2005-10-12 2006-10-12 A jtag testing arrangement for an integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FI20050328U FI7354U1 (fi) 2005-10-12 2005-10-12 Integroidun piirin JTAG-testausjärjestely

Publications (2)

Publication Number Publication Date
FIU20050328U0 FIU20050328U0 (fi) 2005-10-12
FI7354U1 true FI7354U1 (fi) 2007-01-12

Family

ID=35185302

Family Applications (1)

Application Number Title Priority Date Filing Date
FI20050328U FI7354U1 (fi) 2005-10-12 2005-10-12 Integroidun piirin JTAG-testausjärjestely

Country Status (2)

Country Link
FI (1) FI7354U1 (fi)
WO (1) WO2007042622A1 (fi)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2331979B1 (en) * 2008-09-26 2012-07-04 Nxp B.V. Method for testing a partially assembled multi-die device, integrated circuit die and multi-die device
CN102404167B (zh) * 2011-11-03 2014-02-19 清华大学 基于变量依赖的并行扩展有限状态机的协议测试生成方法
CN102707919A (zh) * 2012-05-28 2012-10-03 上海海事大学 一种使用有限状态机控制fifo之间读写的装置及方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6191603B1 (en) * 1999-01-08 2001-02-20 Agilent Technologies Inc. Modular embedded test system for use in integrated circuits
JP2004500712A (ja) * 2000-01-18 2004-01-08 ケイデンス・デザイン・システムズ・インコーポレーテッド 多数の回路ブロックを有するチップ用階層試験回路構造
US7080789B2 (en) * 2003-05-09 2006-07-25 Stmicroelectronics, Inc. Smart card including a JTAG test controller and related methods

Also Published As

Publication number Publication date
FIU20050328U0 (fi) 2005-10-12
WO2007042622A1 (en) 2007-04-19

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