FIU20050328U0 - Integrated Circuit JTAG Test Arrangement - Google Patents

Integrated Circuit JTAG Test Arrangement

Info

Publication number
FIU20050328U0
FIU20050328U0 FI20050328U FIU20050328U FIU20050328U0 FI U20050328 U0 FIU20050328 U0 FI U20050328U0 FI 20050328 U FI20050328 U FI 20050328U FI U20050328 U FIU20050328 U FI U20050328U FI U20050328 U0 FIU20050328 U0 FI U20050328U0
Authority
FI
Finland
Prior art keywords
integrated circuit
test arrangement
jtag test
circuit jtag
arrangement
Prior art date
Application number
FI20050328U
Other languages
Finnish (fi)
Swedish (sv)
Inventor
Mikko Simonen
Ilkka Reis
Original Assignee
Patria Advanced Solutions Oy
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Patria Advanced Solutions Oy filed Critical Patria Advanced Solutions Oy
Priority to FI20050328U priority Critical patent/FI7354U1/en
Publication of FIU20050328U0 publication Critical patent/FIU20050328U0/en
Priority to PCT/FI2006/050438 priority patent/WO2007042622A1/en
Application granted granted Critical
Publication of FI7354U1 publication Critical patent/FI7354U1/en

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318516—Test of programmable logic devices [PLDs]
    • G01R31/318519—Test of field programmable gate arrays [FPGA]
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318558—Addressing or selecting of subparts of the device under test
FI20050328U 2005-10-12 2005-10-12 JTAG testing arrangement for an integrated circuit FI7354U1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FI20050328U FI7354U1 (en) 2005-10-12 2005-10-12 JTAG testing arrangement for an integrated circuit
PCT/FI2006/050438 WO2007042622A1 (en) 2005-10-12 2006-10-12 A jtag testing arrangement for an integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FI20050328U FI7354U1 (en) 2005-10-12 2005-10-12 JTAG testing arrangement for an integrated circuit

Publications (2)

Publication Number Publication Date
FIU20050328U0 true FIU20050328U0 (en) 2005-10-12
FI7354U1 FI7354U1 (en) 2007-01-12

Family

ID=35185302

Family Applications (1)

Application Number Title Priority Date Filing Date
FI20050328U FI7354U1 (en) 2005-10-12 2005-10-12 JTAG testing arrangement for an integrated circuit

Country Status (2)

Country Link
FI (1) FI7354U1 (en)
WO (1) WO2007042622A1 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2331979B1 (en) * 2008-09-26 2012-07-04 Nxp B.V. Method for testing a partially assembled multi-die device, integrated circuit die and multi-die device
CN102404167B (en) * 2011-11-03 2014-02-19 清华大学 Protocol test generating method of parallel expansion finite-state machine based on variable dependence
CN102707919A (en) * 2012-05-28 2012-10-03 上海海事大学 Device and method for controlling FIFO (First In First Out) read-write by using finite state machine (FSM)

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6191603B1 (en) * 1999-01-08 2001-02-20 Agilent Technologies Inc. Modular embedded test system for use in integrated circuits
US6886121B2 (en) * 2000-01-18 2005-04-26 Cadence Design Systems, Inc. Hierarchical test circuit structure for chips with multiple circuit blocks
US7080789B2 (en) * 2003-05-09 2006-07-25 Stmicroelectronics, Inc. Smart card including a JTAG test controller and related methods

Also Published As

Publication number Publication date
WO2007042622A1 (en) 2007-04-19
FI7354U1 (en) 2007-01-12

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