CN102707919A - Device and method for controlling FIFO (First In First Out) read-write by using finite state machine (FSM) - Google Patents

Abstract

The invention discloses a device using a finite state machine to control reading and writing between FIFOs, which includes an image sensor, an FPGA and a DSP chip connected in sequence, and the DSP chip is connected to a host computer through the FPGA, and is characterized in that: the FPGA The read and empty signals of the three FIFOs are all controlled by the FSM finite state machine, and the FSM finite state machine also controls the write and full signals of one FIFO for writing. The beneficial effects of the present invention are: utilize the FSM finite state machine method to convert the control of reading and writing between FIFOs into state control, which simplifies the design process and shortens the design cycle. Compared with the control of reading and writing between traditional FIFOs, the state machine More efficient and stable.

Description

A device and method for controlling reading and writing between FIFOs using a finite state machine

technical field

The present invention relates to a kind of FIFO reading and writing control used for real-time image data transmission data, especially relates to a kind of FIFO reading and a data width of 8 bits based on FPGA in high-resolution scanning imaging Write control of FIFO with data width of 8 bits.

Background technique

In the high-resolution scanning imaging system, the data of the image sensor is received in the FPGA, after the preliminary interpolation operation is completed by the bayer2rgb module to generate 24-bit RGB image data, and then converted into three 8-bit YCbCr data by the rgb2ycbcr module, and transmitted to the core Process chips such as DSP to perform complex digital signal processing operations. After the DSP completes the operation and processing, the image data is transmitted to the FPGA in the same data format. After the FPGA completes the format conversion from YCbCr4:2:2 to 4:4:4 through the deinterleaving and interpolation module, it uses the ycbcr2rgb module to convert the data into three 8 1-bit RGB image data are written into 3 FIFOs respectively, because the final transmission channel interface is composed of a USB controller and a host computer, and the transmission data width of the USB controller is 8 bits. Therefore, before the final transmission, the image data in the three FIFOs must be written in a certain order into a FIFO with a data width of 8 bits for buffering, and then the FPGA controls the USB controller to finally transmit the data to the host computer.

Contents of the invention

The object of the present invention is to provide a kind of device that uses finite state machine to control reading and writing between FIFOs, utilizes FSM finite state machine method to convert the control of reading and writing between FIFOs into state control, simplifies the design process, shortens the design cycle, Compared with the traditional control of reading and writing between FIFOs, the state machine is more efficient and stable.

The technical problem solved by the present invention can adopt following technical scheme to realize:

A device that uses a finite state machine to control reading and writing between FIFOs, it includes sequentially connected image sensors, FPGAs, RGB modules and DSP chips, and the DSP chip is connected to an upper computer through the FPGA, and it is characterized in that: in the FPGA The read and empty signals of the three FIFOs are all controlled by the FSM finite state machine, and the FSM finite state machine also controls the write and full signals of one FIFO for writing.

In an embodiment of the present invention, the data width of the FIFO is 8 bits.

A method of using a finite state machine to control reading and writing between FIFOs, characterized in that the method comprises the steps of:

1) Driven by the clock signal, next state next_state is generated, and at the same time, a clock delay is made for the empty signal empty and the read signal read of the three FIFOs that store BGR data respectively;

2) Under the action of the input signal and the clock, complete the conversion of the current state current_state and the next state next_state, and use the one-hot code one-hot to perform state encoding on the read signal states of the three FIFOs that store BGR data respectively;

3) Under the action of the delayed read signal, the write control of the FIFO for writing data is realized.

The beneficial effects of the present invention are: utilize the FSM finite state machine method to convert the control of reading and writing between FIFOs into state control, which simplifies the design process and shortens the design cycle. Compared with the control of reading and writing between traditional FIFOs, the state machine More efficient and stable.

Description of drawings

Figure 1 is a block diagram of the FSM finite state machine.

Figure 2 is a state transition diagram of the FSM finite state machine.

Figure 3 is a schematic diagram of the connection between the FIFO and the state machine in the FPGA.

Detailed ways

In order to make the technical means, creative features, goals and effects achieved by the present invention easy to understand, the present invention will be further described below in conjunction with specific embodiments.

Referring to Fig. 3, a kind of device that uses finite state machine to control reading and writing between FIFO, it comprises image sensor, FPGA, RGB module and DSP chip that are connected in sequence, and described DSP chip is connected host computer by FPGA, it is characterized in that: all The read and empty signals of the three FIFOs in the FPGA are all controlled by the FSM finite state machine, and the FSM finite state machine also controls the write and full signals of one FIFO for writing.

A method of using a finite state machine to control reading and writing between FIFOs, characterized in that the method comprises the steps of:

1) Driven by the clock signal, next state next_state is generated, and at the same time, a clock delay is made for the empty signal empty and the read signal read of the three FIFOs that store BGR data respectively;

2) Under the action of the input signal and the clock, complete the conversion of the current state current_state and the next state next_state, and use the one-hot code one-hot to perform state encoding on the read signal states of the three FIFOs that store BGR data respectively;

3) Under the action of the delayed read signal, the write control of the FIFO for writing data is realized.

Below in conjunction with Fig. 1 and Fig. 2 respectively, utilize FSM finite state machine to the reading of 3 data widths of 8-bit FIFOs and the control work of a data width of 8-bit FIFOs in this method in the high-resolution scanning imaging system Describe in detail.

This imaging system preprocesses the 2592*1944 (pixel/frame) high-resolution bayer image signal obtained from the image sensor into an RGB color signal, and uses the rgb2ycbcr module and the output timing control module to allow the DSP to complete the core digital signal processing operation of the image After the DSP processing is completed, the image data is transmitted back to the FPGA, and the FPGA converts the image data into 24-bit RGB data through the input timing control module and the ycbcr2rgb module. Since the final data must be transmitted to the upper position by the 8-bit data channel of the USB controller The final splicing and processing are performed by the FPGA, so the FPGA first stores 24-bit RGB data into three asynchronous FIFOs, and then the FSM finite state machine controls the reading of the three FIFOs and the writing of the FIFOs connected to the USB controller to complete the three The 8-bit RGB data is transmitted in the order of the BMP file (8-bit B first, then 8-bit G, and then 8-bit R data), until the entire image data is transmitted in this order.

In the next-state logic of the structural block diagram of the FSM finite state machine in Figure 1, an asynchronous reset is used. If the reset signal is valid, the state is the initial state state_B; under the action of the clock signal, the conversion between the current state and the next state is completed, and at the same time The empty signals empty_B, empty_G, and empty_R of the current three storage data FIFOs are respectively saved by six one-bit shift registers, which are respectively empty_B_d, empty_G_d, empty_R_d and the read signals read_en_B, reda_en_G, and read_en_R of the current three storage data FIFOs, respectively. for read_en_B_d, read_en_G_d, read_en_R_d.

The function completed by the state register in the structural block diagram of the FSM finite state machine in Fig. 1 can be described by the state transition diagram of the FSM finite state machine in Fig. 2:

1) The default current state is that the initial state is state_B. If the FIFO storing data B is empty, that is, empty_B is 1, the next state is still state_B, that is, read_B_en is set to 0, read_G_en is set to 0, read_R_en is set to 0, and the waiting function is completed No data is read. If there is data in the FIFO storing data B, that is, when empty_B is 0, if the FIFO to be written into the data is not full, read the FIFO storing data B, that is, read_B_en is set to 1, read_G_en is set to 0, read_G_en is set to 0, and the first step is completed The read function of data B, and enter the next state of reading data, namely state_G. Otherwise, the next state is still state_B, read_B_en is set to 0, read_G_en is set to 0, and read_R_en is set to 0, that is, wait for the FIFO ready to write data to become writable before starting to read data B.

2) When the state state_B is completed and enters the state state_G, if the FIFO to be written into the data is not full, read the FIFO storing the data G, that is, set read_B_en to 0, read_G_en to 1, and read_R_en to 0 to complete the second data G read function, and enter the next state of reading data, namely state_R. Otherwise, the next state is still state_G, read_B_en is set to 0, read_G_en is set to 0, and read_R_en is set to 0, that is, wait for the FIFO ready to write data to become writable before starting to read data G.

3) When the state state_G is completed and enters the state state_R, if the FIFO to be written into the data is not full, read the FIFO storing the data R, that is, read_B_en is set to 0, read_G_en is set to 0, read_R_en is set to 1, and the third data R is completed read function, and enter the next state of reading data, namely state_B. Otherwise, the next state is still state_R, read_B_en is set to 0, read_G_en is set to 0, and read_R_en is set to 0, that is, wait for the FIFO ready to write data to become writable before starting to read data R.

4) Repeat the above process to complete the read control of 3 FIFOs storing image data BGR.

The output logic in the structural block diagram of the FSM finite state machine in Figure 1 completes the data writing of the final write FIFO and the control of the write signal wr_end:

1) When the read data of the FIFO storing the B data is completed, that is, when read_en_B_d is 1, the write signal wr_end of the FIFO writing the data is set to 1, and the data B is written at the same time.

2) When the read data of the FIFO storing G data is completed, that is, when read_en_G_d is 1, the write signal wr_end of the FIFO for writing data is set to 1, and the data G is written at the same time.

3) When read_en_R_d is 1 after the FIFO that stores R data reads data, the write signal wr_end of the FIFO that writes data is set to 1, and data R is written at the same time.

4) Repeat the above process to complete the sequential writing of image data BGR into FIFO.

The basic principles and main features of the present invention and the advantages of the present invention have been shown and described above. Those skilled in the industry should understand that the present invention is not limited by the above-mentioned embodiments. What are described in the above-mentioned embodiments and the description only illustrate the principle of the present invention. Without departing from the spirit and scope of the present invention, the present invention will also have Variations and improvements are possible, which fall within the scope of the claimed invention. The protection scope of the present invention is defined by the appended claims and their equivalents.

Claims (3)

1. A device that uses a finite state machine to control reading and writing between FIFOs, it includes an image sensor, an FPGA and a DSP chip that are connected in sequence, and the DSP chip is connected to an upper computer through an FPGA, and it is characterized in that, in the FPGA, 3 The read and empty signals of the FIFO used for reading are controlled by the FSM finite state machine, and the FSM finite state machine also controls the write and full signals of a FIFO used for writing. 2. A device for using a finite state machine to control reading and writing between FIFOs to complete data transmission according to claim 1, wherein the data width of the FIFOs is 8 bits. 3. a method of using finite state machine to control reading and writing between FIFO, it is characterized in that, described method comprises the steps: 1) Driven by the clock signal, the next state next_state is generated, and at the same time, a clock delay is made for the empty signal empty and the read signal read of the three FIFOs that store BGR data respectively; 2) Under the action of the input signal and the clock, complete the conversion of the current state current_state and the next state next_state, and use the one-hot code one-hot to perform state encoding on the read signal states of the three FIFOs that store BGR data respectively; 3) Under the action of the delayed read signal, the write control of the FIFO for writing data is realized.

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