CN112650468A - Zero-delay FIFO circuit and electronic equipment - Google Patents

Zero-delay FIFO circuit and electronic equipment Download PDF

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Publication number
CN112650468A
CN112650468A CN202011401340.7A CN202011401340A CN112650468A CN 112650468 A CN112650468 A CN 112650468A CN 202011401340 A CN202011401340 A CN 202011401340A CN 112650468 A CN112650468 A CN 112650468A
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fifo
ram
zero
data
circuit
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CN112650468B (en
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文湘鄂
徐辉
东健慧
王世超
张磊
刘洋
束文韬
宋磊
贾惠柱
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Beijing Boya Huishi Intelligent Technology Research Institute Co ltd
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Beijing Boya Huishi Intelligent Technology Research Institute Co ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory

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Abstract

The application discloses a zero-delay FIFO circuit and electronic equipment, wherein the zero-delay FIFO circuit comprises a data channel and a state machine; the state machine is respectively in communication connection with the RAM FIFO, the first multi-path gate and the second multi-path gate in the data channel, and outputs a control signal according to the states of the data in the RAM FIFO, the first register group and the second register group so as to finish the operation that the data which enters the FIFO circuit firstly is read. Compared with the prior art, the zero-delay FIFO circuit is realized by the two stages of register groups and the RAM FIFO through the control of the state machine, so that the FIFO circuit has the advantages of large capacity and convenience in use.

Description

Zero-delay FIFO circuit and electronic equipment
Technical Field
The application belongs to the technical field of circuit design, and particularly relates to a zero-delay FIFO circuit and electronic equipment.
Background
A FIFO (First _ In _ First _ Out) is a basic device that is widely used In digital circuit design. The FIFO is typically empty, full signal as output, clock, reset, read, write signals as input, FIFO's basic function is to store data, and incoming data is first taken by downstream logic.
The FIFO has to store data with a storage unit, usually the FIFO with a narrow bit width and a shallow depth, and the register is used as the storage unit, although the unit area of the register is large (relative to a bit unit of a RAM (Random Access Memory)), the value of the register can be read out without setting an address or a read enable signal in advance, so that the output data of the FIFO built by the register can be sampled by downstream logic when the empty signal is low (namely the FIFO is not empty), and the FIFO is not related to the state of the currently input read signal, which is called as a zero-delay FIFO.
The zero-delay FIFO design enables downstream sampling logic to be designed simply (the combinational logic can be realized), however, for the case that the memory cell is in more demand, if the FIFO is realized only by a register group, the area overhead of the FIFO is very large, so the memory cell has to be constructed by a synchronous RAM with much smaller area overhead, because the common synchronous RAM requires that a read enable address and a read address must be set one clock cycle ahead of time to give valid data in the following clock cycle, the read signal of the FIFO must be set at the same time when the downstream sampling logic detects that the FIFO empty signal is pulled down, the output of the FIFO can be correctly sampled in the next beat, and the downstream sampling logic is required to design the sequential logic to read the FIFO, that is, the complexity of the downstream sampling logic is increased. Since such a FIFO has a one-beat read-out delay, it is classified as a non-zero delay FIFO. In the present application, the memory unit is composed of a RAM, and a FIFO with a one-beat read-out delay is referred to as a RAM FIFO, and since its design is common, specific details of its design are not given here. In summary, the two prior art FIFO designs have limitations.
Disclosure of Invention
In view of the above, embodiments of the present application provide a zero-delay FIFO circuit and an electronic device to overcome the problems in the prior art.
An embodiment of a first aspect of the present application provides a zero-delay FIFO circuit, including:
a data channel and a state machine; one end of the data channel is connected with the data input end of the FIFO circuit, and the other end of the data channel is connected with the data output end of the FIFO circuit; the state machine is respectively connected with an empty signal end, a full signal end, a read signal end and a write signal end of the FIFO circuit;
the data channel comprises an RAM FIFO, a first multi-path strobe, a first register group, a second multi-path strobe and a second register group;
the state machine is respectively in communication connection with the RAM FIFO, the first multi-path gate and the second multi-path gate, and outputs a control signal according to the states of data in the RAM FIFO, the first register group and the second register group so as to finish the operation that the data which firstly enters the FIFO circuit is read firstly.
According to some embodiments of the present application, the first multiplexer is communicatively coupled to the RAM FIFO, the first register bank, and the state machine, respectively;
the second multiplexer is in communication with the RAM FIFO, the second register bank, and the state machine, respectively.
According to some embodiments of the present application, a data input of the FIFO circuit is connected to the RAM FIFO, the first multiplexer, and the second multiplexer, respectively;
and the data output end of the FIFO circuit is respectively connected with the second multi-path gate and the second register group.
According to some embodiments of the application, the RAM FIFO comprises: the device comprises an RAM FIFO input end, an RAM FIFO output end, an RAM FIFO empty signal end, an RAM FIFO full signal end, an RAM FIFO read signal end and an RAM FIFO write signal end.
According to some embodiments of the application, the RAM FIFO input is connected to a data input of the FIFO circuit.
According to some embodiments of the present application, the RAM FIFO output is connected to the first and second muxes, respectively.
According to some embodiments of the present application, the RAM FIFO empty signal terminal, the RAM FIFO full signal terminal, the RAM FIFO read signal terminal, and the RAM FIFO write signal terminal are all connected to the state machine.
An embodiment of a second aspect of the present application provides an electronic device comprising a zero-delay FIFO circuit as described in the first aspect.
The application provides a zero-delay FIFO circuit and an electronic device, wherein the zero-delay FIFO circuit comprises a data channel and a state machine; the state machine is respectively in communication connection with the RAM FIFO, the first multi-path gate and the second multi-path gate in the data channel, and outputs a control signal according to the states of the data in the RAM FIFO, the first register group and the second register group so as to finish the operation that the data which enters the FIFO circuit firstly is read. Compared with the prior art, the zero-delay FIFO circuit is realized by the two stages of register groups and the RAM FIFO through the control of the state machine, so that the FIFO circuit has the advantages of large capacity and convenience in use.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the application. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:
FIG. 1 is a schematic diagram of a zero-delay FIFO circuit according to an embodiment of the present application;
fig. 2 is a schematic diagram of a state machine provided in an embodiment of the present application.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
These and other aspects of embodiments of the present application will be apparent from and elucidated with reference to the following description and drawings. In the description and drawings, particular embodiments of the application are disclosed in detail as being indicative of some of the ways in which the principles of the embodiments of the application may be practiced, but it is understood that the embodiments of the application are not limited correspondingly in scope. On the contrary, the embodiments of the application include all changes, modifications and equivalents coming within the spirit and terms of the claims appended hereto.
The zero-delay FIFO circuit and the electronic device according to the embodiments of the present application are described below with reference to the drawings.
First, a zero-delay FIFO circuit proposed in an embodiment of the present application will be described. Fig. 1 is a schematic diagram of a zero-delay FIFO circuit according to an embodiment of the present application.
As shown in fig. 1, a zero-delay FIFO circuit (hereinafter referred to as FIFO circuit) provided in the embodiment of the present application includes: a data channel 100 and a State Machine (FSM) 200.
One end of the data channel 100 is connected to the data input terminal (DIN terminal in the figure) of the FIFO circuit, and the other end is connected to the data output terminal (DOUT terminal in the figure) of the FIFO circuit;
the state machine 200 is respectively connected to the EMPTY signal terminal (EMPTY terminal in the figure), the FULL signal terminal (FULL terminal in the figure), the read signal terminal (RD terminal in the figure) and the write signal terminal (WR terminal in the figure) of the FIFO circuit;
the data channel 100 includes a RAM FIFO110, a first multiplexer 120, a first register bank 130, a second multiplexer 140, and a second register bank 150; the state machine 200 is respectively connected to the RAM FIFO110, the first multi-way gate 120, and the second multi-way gate 140 in a communication manner, and the state machine 200 is configured to output a control signal according to the states of the data in the RAM FIFO110, the first register group 130, and the second register group 150, so as to complete an operation in which the data that enters the FIFO circuit first is read first.
The first multiplexer 120 is communicatively coupled to the RAM FIFO110, the first register bank 130, and the state machine 200, respectively, and outputs data from the RAM FIFO110 to the first register bank 130 under control of the state machine 200.
The second multiplexer 140 is communicatively coupled to the RAM FIFO110, the second register set 150, and the state machine 200, respectively, and outputs data from the RAM FIFO110, the first register set 130, to the second register set 150 under control of the state machine 200.
In the present application, the input to the RAM FIFO110 can only be the data input to the zero-delay FIFO circuit. While the data output of the zero-delay FIFO circuit is driven directly by the second register set 150. All data flow in between, the reading and writing of the RAM FIFO110, and the state of the zero-delay FIFO circuit are controlled by the state machine 200.
In the present application, the control of the state machine 200 can selectively skip the data in the RAM FIFO110 or not, and directly store the data in the first register set 130 or the second register set 150, thereby reducing the delay of data transmission.
The data input end of the FIFO circuit is respectively connected with the RAM FIFO110, the first multi-way gate 120 and the second multi-way gate 140;
the data output terminals of the FIFO circuits are connected to the second multiplexer 140 and the second register group 150, respectively.
Specifically, the RAM FIFO110 includes: a RAM FIFO input terminal (din terminal shown in the figure), a RAM FIFO output terminal (dout terminal shown in the figure), a RAM FIFO empty signal terminal (empty terminal shown in the figure), a RAM FIFO full signal terminal (full terminal shown in the figure), a RAM FIFO read signal terminal (rd terminal shown in the figure), and a RAM FIFO write signal terminal (wr terminal shown in the figure).
Specifically, the input end of the RAM FIFO is connected with the data input end of the FIFO circuit, such as the DIN end and the DIN end in the figure.
Specifically, the output port (dout port in the figure) of the RAM FIFO is connected to the first multiplexer 120 and the second multiplexer 140, respectively.
Specifically, a RAM FIFO empty signal terminal, a RAM FIFO full signal terminal, a RAM FIFO read signal terminal, and a RAM FIFO write signal terminal are all connected to the state machine 200. An empty terminal, a full terminal, an rd terminal and a wr terminal as shown in the figure are all connected with the state machine 200.
Fig. 2 is a schematic diagram of a state machine according to an embodiment of the present application.
As shown in fig. 2, the state machine used in the present application has four states, such as ST _ EMPTY state, ST _ AC state, ST _ a state, and ST _ AB state, and other state machine designs are possible because the state machine design is often related to the user himself, and the use of other state machine designs or the use of a state machine without explicit should not affect the coverage effectiveness of the present application.
In fig. 2, a is the second register group 150, B is the first register group 130, C is the register group built in the RAM FIFO110, it should be noted that, unlike the two physical register groups of A, B, C is only a register group assumed to exist inside the RAM _ FIFO for the purpose of illustrating the design principle, because the RAM _ FIFO must be delayed by one beat to read the result, and for the sake of analysis, the RAM _ FIFO can be functionally equivalent to a 0-delayed FIFO with the addition of a stage of output register, that is, the C register group.
The color of the box in fig. 2 represents the status of the data in A, B, C, the white blocks represent no valid data, and the black blocks represent the presence of valid data. Such as ST _ EMPTY state, A, B, C has no valid data; for example, the ST AC state represents A, C valid data, and B has no valid data. The symbols in fig. 2 illustrate: ST _ EMPTY indicates a state where A, B and the C register set are both EMPTY; ST _ A indicates the state that the A register set is effective and the B, C register set is empty; ST _ AB indicates A, B register set valid, C register set empty state; ST _ AC indicates A, C register set valid, B register set empty state; WR represents the module port write signal, high active; RD represents module port read signal, high valid; empty indicates the internal RAM FIFO (110) is empty, high indicating that the internal RAM FIFO is empty.
For the data state in C, if the empty end of the current beat RAM FIFO110 is low while the rd signal end is pulled high by the state machine 200, then the output of the next beat RAM FIFO110, i.e., the data in C, is valid data.
It should be noted that, in the present application, it can be assumed that the valid data only lasts for one clock cycle, because although the output port of a considerable part of the RAM can maintain the original value when it is not being read (i.e. the read enable is set low), there is actually a large amount of RAM operating in the so-called "write first" mode, which means that even if the read enable is not set, a RAM write operation can change the output data on the port. Considering that the correct RAM FIFO110 design will not read and write the same RAM address at the same time (i.e. there will be no read-write collision), it can be sure that valid data is always present at the dout terminal of the RAM FIFO110 in the clock cycle after the empty terminal of the RAM FIFO110 is low and the rd signal terminal is pulled high.
Note that, in fig. 2, the internal signal and the external output that need to be updated in each state are not all marked.
Specifically, the zero-delay FIFO circuit of the present application, under the control of the state machine 200, automatically switches input data to a corresponding storage module according to the storage state of the storage module, thereby implementing a data zero-delay FIFO.
The zero-delay FIFO circuit comprises a data channel and a state machine; the state machine is respectively in communication connection with the RAM FIFO, the first multi-path gate and the second multi-path gate in the data channel, and outputs a control signal according to the states of the data in the RAM FIFO, the first register group and the second register group so as to finish the operation that the data which enters the FIFO circuit firstly is read. Compared with the prior art, the zero-delay FIFO circuit is realized by the two stages of register groups and the RAM FIFO through the control of the state machine, so that the FIFO circuit has the advantages of large capacity and convenience in use; the FIFO circuit can also operate at a higher clock frequency because the register output timing is better than the RAM port output directly.
An embodiment of the present application further provides an electronic device, which includes the zero-delay FIFO circuit in the above embodiment.
While the embodiments of the present application have been described in detail with reference to the accompanying drawings, the embodiments of the present application are not limited to the details of the embodiments, and various simple modifications can be made to the technical solutions of the embodiments of the present application within the technical concept of the embodiments of the present application, and the simple modifications all belong to the protection scope of the embodiments of the present application.
It should be noted that the various features described in the above embodiments may be combined in any suitable manner without departing from the scope of the invention. In order to avoid unnecessary repetition, the embodiments of the present application do not separately describe various possible combinations.
In addition, any combination of various different implementation manners of the embodiments of the present application can be performed, and the embodiments of the present application should be considered as disclosed in the embodiments of the present application as long as the combinations do not depart from the spirit of the embodiments of the present application.

Claims (8)

1. A zero-delay FIFO circuit, comprising: a data channel and a state machine;
one end of the data channel is connected with the data input end of the FIFO circuit, and the other end of the data channel is connected with the data output end of the FIFO circuit; the state machine is respectively connected with an empty signal end, a full signal end, a read signal end and a write signal end of the FIFO circuit;
the data channel comprises an RAM FIFO, a first multi-path strobe, a first register group, a second multi-path strobe and a second register group;
the state machine is respectively in communication connection with the RAM FIFO, the first multi-path gate and the second multi-path gate, and outputs a control signal according to the states of data in the RAM FIFO, the first register group and the second register group so as to finish the operation that the data which firstly enters the FIFO circuit is read firstly.
2. The zero-delay FIFO circuit of claim 1, wherein the first multiplexer is communicatively coupled to the RAM FIFO, the first register bank, and the state machine, respectively;
the second multiplexer is in communication with the RAM FIFO, the second register bank, and the state machine, respectively.
3. The zero-delay FIFO circuit of claim 2, wherein a data input of the FIFO circuit is connected to the RAM FIFO, the first mux, and the second mux, respectively;
and the data output end of the FIFO circuit is respectively connected with the second multi-path gate and the second register group.
4. The zero-delay FIFO circuit of claim 3, wherein the RAM FIFO comprises: the device comprises an RAM FIFO input end, an RAM FIFO output end, an RAM FIFO empty signal end, an RAM FIFO full signal end, an RAM FIFO read signal end and an RAM FIFO write signal end.
5. The zero-delay FIFO circuit of claim 4 wherein the RAM FIFO input is connected to the data input of the FIFO circuit.
6. The zero-delay FIFO circuit of claim 4, wherein the RAM FIFO output is connected to the first and second muxes, respectively.
7. The zero-delay FIFO circuit of claim 4 wherein the RAM FIFO empty signal terminal, the RAM FIFO full signal terminal, the RAM FIFO read signal terminal and the RAM FIFO write signal terminal are all connected to the state machine.
8. An electronic device comprising a zero-delay FIFO circuit according to any of claims 1-7.
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