KR200211287Y1 - High speed first in, first out memory - Google Patents

Abstract

The present invention relates to a high-speed first-in, first-out memory. In the case of writing and reading conventional data into the first-in-first-out memory, a completion signal is output after performing the writing and reading operation to the last address. There is a problem in that the system efficiency is not suitable for. Accordingly, the present invention has been made to solve the above-mentioned conventional problems, the first flip-flop unit for receiving the output of the write count unit to the input terminal by the write bar signal applied to the clock terminal and sequentially outputs it; A second flip-flop unit which receives the output of the read count unit to the input terminal by the read bar signal applied to the clock stage and sequentially outputs the read count unit; An upper comparator comparing the upper output signals of the first and second flip-flop parts and outputting a high potential if they are the same; A lower comparator for comparing the lower output signals of the first and second flip-flop parts and outputting high potentials if they are the same; A device configured as an output unit which receives the output signal of the upper comparator and the lower comparator and outputs a completion signal according to the read bar signal, outputs a completion signal before writing and reading to the last address of the first-in first-out memory. In addition, the state of the first-in, first-out memory is detected one clock early to be coupled to high-speed operation, thereby improving the operation performance of the system.

Description

High speed first in, first out memory

The present invention relates to a high-speed first-in, first-out memory, and more particularly, to a high-speed first-in, first-out memory that detects an empty flag state of the first-in first-out memory and improves the operation speed of the entire system.

FIG. 1 is a block diagram illustrating a general high-speed first-in first-out memory. As shown in FIG. 1, a write bar signal for writing input data into the first-in first-out memory is shown in FIG. Write counting unit 10 for receiving the input and counting; Read bar signal for reading data of the first-in first-out memory ( Read counting unit 20 for receiving and counting; The comparator 30 receives the output signals WCS and RCS of each of the write counter 10 and the read counter 10, and compares them to output a completion signal EF.

FIG. 2 is a circuit diagram of a comparator in a conventional high-speed first-in first-out memory. As shown in FIG. A first flip-flop unit 40 which receives the output WCS of the write counting unit 10 through the input terminal D and sequentially outputs the output WCS; Read bar signal applied to clock stage A second flip-flop unit 50 which receives the output RCS of the read counter 20 through the input terminal D and sequentially outputs the output RCS to the input terminal D; A plurality of non-exclusive OR gates 61, 62, 63, and 64 for comparing the output signals of the first and second flip-flop units 40 and 50 and outputting high potentials when they are the same. Wow; And a logical AND gate 70 which receives the output signals of the plurality of non-exclusive logical OR gates 61, 62, 63, and 64 and performs logical AND operation on the output signals. The two flip-flop units 40 and 50 receive output signals WCS and RCS, respectively, and write the write bar signals of the clock stages. ) And read bar signal ( A plurality of deflip-flops (41, 42, 43, 44) (51, 52, 53) output to the input terminals of the plurality of non-exclusive OR gates 61, 62, 63, and 64 by 54), the operation process according to the prior art configured as described above will be described in detail.

First, in order to write data to the first-in first-out memory, the write bar signal ( ) And read bar signal (for reading data) Are generated respectively, the write bar signal ( ), The write counting unit 10 receives input data into the first-in first-out memory as the address is sequentially increased by 1, and the read bar signal ( Read count unit 20 reads the input data while sequentially increasing the address by one.

Therefore, each write bar signal ( ) And read bar signal ( ), The first and second flip-flop units 40 and 50 output the output addresses of the write count unit 10 and the read count unit 20, and the plurality of ratios of the output signals are received. Exclusive-OR gates 60, 61, 62, and 63 are non-exclusive.

Therefore, the plurality of non-exclusive OR gates 60, 61, 62, and 63 output high potentials when the output addresses of the input write coefficient unit 10 and the read coefficient unit 20 are the same. Done.

Accordingly, the AND gate 70 receiving the output signals of the plurality of non-exclusive OR gates 60, 61, 62, and 63 performs an AND operation on the output signals of the plurality of non-exclusive OR gates 60, 61, 62, and 63. The input data is written to the selection memory, and it is determined that the read operation is completed, and the completion signal EF is output.

That is, the comparator 30 receives the output addresses of the write counter 10 and the read counter 20, compares them, and outputs the completion signal EF to output the next input data to the first-in first-out memory. Will be written to

In the case of writing and reading the conventional data into the first-in, first-out memory as described above, the completion signal is output after performing the writing and reading operation up to the last address, which takes more than a predetermined time, which is not suitable for a high-speed operation system, resulting in inefficient system efficiency. There was a problem.

Therefore, the present invention has been devised to solve the above-mentioned problems. The complete signal is output before the write and read operation to the last address, and the empty flag state of the first-in first-out memory is detected to detect the entire system. It is an object of the present invention to provide a high-speed first-in, first-out memory with improved operation speed.

1 is a block diagram showing the configuration of a general fast first-in first-out memory;

2 is a circuit diagram of a comparison unit in a conventional fast first-in first-out memory.

3 is a circuit diagram of a comparator in the high-speed first-in first-out memory of the present invention.

* Description of the symbols for the main parts of the drawings *

40,50: flip-flop portion 41-44, 51-54: flip-flop

100: upper comparison unit 101,102,111,112: non-exclusive logical gate

103,107,113,118: logical sum gate 104,114: inverter

105,106,115,116: Transmission gate 117,121: Logic gate

110: lower comparison unit 120: output unit

122,123: negative AND gate

The high-speed first-in first-out memory of the present invention for achieving the above object comprises a first flip-flop unit for receiving the output of the write count unit to the input stage by the write bar signal applied to the clock stage and sequentially outputting the output; A second flip-flop unit which receives the output of the read count unit to the input terminal by the read bar signal applied to the clock stage and sequentially outputs the read count unit; An upper comparator comparing the upper output signals of the first and second flip-flop parts and outputting a high potential if they are the same; A lower comparator for comparing the lower output signals of the first and second flip-flop parts and outputting high potentials if they are the same; And an output unit configured to receive an output signal of the upper comparator and the lower comparator and output a completion signal according to the read bar signal.

Hereinafter, with reference to the accompanying drawings, the operation and effect of an embodiment of the present invention will be described in detail.

3 is a circuit diagram of a comparator in the high-speed first-in first-out memory of the present invention, as shown in FIG. A first flip-flop unit 40 which receives the output WCS of the write counting unit 10 through the input terminal D and sequentially outputs the output WCS; Read bar signal applied to clock stage A second flip-flop unit 50 which receives the output RCS of the read counter 20 through the input terminal D and sequentially outputs the output RCS to the input terminal D; An upper comparator 100 for receiving the upper output signals of the first and second flip-flop units 40 and 50 and comparing the upper output signals and outputting high potentials if they are the same; A lower comparator 110 which receives the lower output signals of the first and second flip-flop units 40 and 50 and compares them and outputs high potentials if they are the same; The read bar signal receives the output signal of the upper comparator 100 and the lower comparator 110 ( And an output unit 120 for outputting a completion signal EF, and the first and second flip-flop units 40 and 50 respectively correspond to a write bar signal of a clock stage. ) And read bar signal ( ), A plurality of deflip-flops 41, 42, 43, 44 (51, 52, 53, 54) for outputting the output signal WCS (RCS) of the input terminal to the output terminal.

The upper comparator 100 includes: a first non-exclusive logic sum gate 101 which receives the output signals of the first and second flip-flops 41 and 51 and outputs them by performing non-exclusive logic operation on the output signals; A second non-exclusive OR gate 102 for receiving the output signals of the second deflip-flop 42 and the fifth def- flip-flop 51 and outputting the non-exclusive-OR operation; A first AND gate 103 for receiving an output signal of the first and second non-exclusive OR gates 101 and 102 and performing an OR operation on the output signal; An inverter 104 for inverting and outputting an output signal of the sixth flip-flop 52; An output signal of the first non-exclusive logic sum gate 101 which receives an output signal of the inverter 104 as a non-inverting terminal, receives an output signal of the sixth flip-flop 52 as an inverting terminal, and outputs an output signal of the first non-exclusive logic sum gate 101; 1 transmission gate 105; An output signal of the second non-exclusive logic sum gate 102 which receives an output signal of the inverter 104 as an inverting terminal and receives an output signal of the sixth flip-flop 52 as a non-inverting terminal; 2 transmission gates 106; The second logical sum gate 107 receives the output signals of the first and second transfer gates 105 and 106 and performs a logical sum operation on the output signals. The lower comparator 110 includes a third deflip-flop. A first non-exclusive OR gate 111 for receiving an output signal of the 43 and the seventh flip-flop 53 and outputting the non-exclusive OR operation; A second non-exclusive OR gate 112 for receiving the output signals of the fourth deflip-flop 44 and the seventh flip-flop 53, and outputting the non-exclusive OR operation; A first AND gate 113 for receiving an output signal of the first and second non-exclusive OR gates 111 and 112 and performing an OR operation on the output signals; An inverter 114 for inverting and outputting an output signal of the eighth flip-flop 54; An output signal of the first non-exclusive logic sum gate 111 which receives an output signal of the inverter 114 as a non-inverting terminal, receives an output signal of the eighth deflip-flop 54 as an inverting terminal, and outputs an output signal of the first non-exclusive logic sum gate 111; 1 transmission gate 115; An output signal of the second non-exclusive logic sum gate 112 by receiving an output signal of the inverter 114 as an inverting terminal and receiving an output signal of the eighth flip-flop 54 as a non-inverting terminal; 2 transmission gates 116; An AND gate 117 for receiving the output signals of the seventh and eighth flip-flops 53 and 54 and performing logical AND operation on the output signals; And a second OR gate 118 that receives the output signals of the first and second transfer gates 115 and 116 and the output signal of the AND gate 117 and performs an OR operation on the output signals.

In addition, the output unit 120 receives an output signal of the upper comparator 100 and the lower comparator 110 and the logical AND gate 121 for performing an AND operation on the output signal; The output signal of the AND gate 121 and the read bar signal ( ) And the first and second negative AND gates 122 and 123 for latching the same), and the operation of an embodiment according to the present invention configured as described above will be described in detail.

First, in order to write data to the first-in first-out memory, the write bar signal ( ) And read bar signal (for reading data) Are generated respectively, the write bar signal ( ), The write counting unit 10 receives the input data into the first-in first-out memory by sequentially increasing the address by one, and reads the read bar signal ( Read count unit 20 reads the input data while sequentially increasing the address by one.

Accordingly, each write bar signal ( ) And read bar signal ( ), The first and second flip-flop units 40 and 50 output the output addresses of the write count unit 10 and the read count unit 20.

Therefore, the output addresses of the write counter 10 and the read counter 20 are divided into upper 2 bits and lower 2 bits and input to the upper comparator 100 and the lower comparator 110.

In the case of the upper comparator 100, the first non-exclusive logic gate 101 receives an output signal of the first deflip-flop 41 and the fifth def- flip-flop 51, and calculates the non-exclusive logic operation. And a second non-exclusive OR gate 102 to receive an output signal from the second deflip-flop 42 and the fifth def- flip-flop 51, and output the non-exclusive-OR. The first AND gate 103, which has received the output signals of the first and second non-exclusive OR gates 101 and 102, performs an OR operation on the output signals.

Here, the output signal of the first non-exclusive OR gate 101 or the first OR gate 103 through the first and second transfer gates 105 and 106 by the output signal of the sixth flip-flop 52. Selects and outputs an output signal, and the second OR gate 107 receiving the output signals of the first and second transfer gates 105 and 106 performs an OR operation on the output signal to the output unit 120. .

In addition, in the case of the lower comparison unit 110, the non-exclusive logic sum gate 111 receives an output signal of the third deflip-flop 43 and the seventh flip-flop 53, and outputs the non-exclusive logic sum. In addition, the non-exclusive OR gate 112 receives the output signals of the fourth deflip flop 44 and the seventh def flip-flop 53, and outputs the non-exclusive logical OR. The first OR gate 113, which has received the output signals of the gates 111 and 112, performs an OR operation on the output signal.

Here, the output signal of the non-exclusive OR gate 111 or the output signal of the first OR gate 113 is transmitted through the plurality of transfer gates 115 and 116 by the output signal of the eighth flip-flop 54. After selecting and outputting, the AND gate 117 receives the output signals of the seventh and eighth flip-flops 53 and 54 and performs an AND operation on the output signals.

Accordingly, the second AND gate 107 that receives the output signal of the first and second transfer gates 115 and 116 and the output signal of the AND gate 117 performs an OR operation on the output unit 120. )

Therefore, the output unit 120 receives the output signals of the upper comparator 100 and the lower comparator 110 and performs an AND operation on the AND gates 121 to perform a logical AND operation on the AND gates 121. 123 using the read bar signal ( And the read bar signal ( Outputs a completion signal (EF) when the

That is, when the address of the write counting unit 10 is 0001 and the address of the read counting unit 20 is 0000, a plurality of non-exclusive logical sum gates of the upper comparison unit 100 that have received the low potential, respectively, Each of the 101 and 102 outputs a low potential, so that the upper comparator 100 outputs a low potential, and the plurality of non-exclusive logic gates 111 and 112 of the lower comparator 110 respectively have a low potential. Since the low comparator 110 outputs a high potential because the high potential is output, the completion signal EF of the output unit 120 is low potential.

Therefore, since the addresses of the write counting unit 10 and the read counting unit 20 sequentially increase by 1, the address of the write counting unit 10 is 1111, and the address of the read counting unit 20 is 1110. In this case, all of the plurality of non-exclusive OR gates 101, 102, 111, and 112 output high potentials.

Therefore, the completion signal EF of the output unit 120 is output at high potential and the next input data is written to the first-in first-out memory.

As described in detail above, the present invention outputs a completion signal before performing a write and read operation to the last address of the first-in first-out memory, so that the state of the first-in first-out memory can be detected by one clock and connected to a high speed operation. There is an effect of improving the operating performance.

Claims (4)

A first flip-flop unit which receives an output of the write count unit to an input terminal by a write bar signal applied to a clock terminal and sequentially outputs the output from the write count unit; A second flip-flop unit which receives the output of the read count unit to the input terminal by the read bar signal applied to the clock stage and sequentially outputs the read count unit; An upper comparator comparing the upper output signals of the first and second flip-flop parts and outputting a high potential if they are the same; A lower comparator for comparing the lower output signals of the first and second flip-flop parts and outputting high potentials if they are the same; And an output unit configured to receive an output signal of the upper comparator and the lower comparator and output a completion signal according to the read bar signal. The gate driving circuit of claim 1, wherein the upper comparator comprises: a first non-exclusive OR gate configured to receive output signals of the first and second flip-flops and output a non-exclusive OR operation; A second non-exclusive logic sum gate configured to receive an output signal of the second flip-flop and the fifth def flip-flop, and output the non-exclusive logic sum; A first AND gate for receiving an output signal of the first and second non-exclusive OR gates and performing an OR operation on the output signals; An inverter for inverting and outputting an output signal of a sixth flip-flop; A first transmission gate configured to receive an output signal of the inverter as a non-inverting terminal, receive an output signal of the sixth flip-flop as an inverting terminal, and output an output signal of the first non-exclusive logic sum gate; A second transfer gate configured to receive an output signal of the inverter as an inverting terminal and receive an output signal of the sixth flip-flop as a non-inverting terminal and output an output signal of the second non-exclusive logic sum gate; And a second logic sum gate configured to receive the output signals of the first and second transfer gates and to perform a logical sum operation on the output signals. The gate driving circuit of claim 1, wherein the lower comparison unit comprises: a first non-exclusive OR gate configured to receive output signals of the third and seventh flip-flops and output the non-exclusive OR operations; A second non-exclusive logic sum gate configured to receive an output signal of a fourth flip-flop and the eighth flip-flop, and output the non-exclusive logic sum; A first AND gate for receiving an output signal of the first and second non-exclusive OR gates and performing an OR operation on the output signals; An inverter for inverting and outputting an output signal of an eighth flip-flop; A first transfer gate configured to receive an output signal of the inverter as a non-inverting terminal and receive an output signal of the eighth flip-flop as an inverting terminal and output an output signal of the first non-exclusive logic sum gate; A second transfer gate configured to receive an output signal of the inverter as an inverting terminal, receive an output signal of the eighth flip-flop as a non-inverting terminal, and output an output signal of the second non-exclusive logic sum gate; An AND gate receiving the output signal of the seventh and eighth flip-flops and performing OR logical operation on the output signal; And a second logical sum gate configured to receive the output signal of the first and second transfer gates and the output signal of the logical multiply gate and perform a logical sum operation on the output signal. The gate driving circuit of claim 1, wherein the output unit comprises: an AND gate receiving the output signal of the upper comparator and the lower comparator and performing logical AND operation on the output signals; And a first and a second negative AND gate receiving the output signal and the read bar signal of the AND gate, and latching them.