CN104599227B - DDR3 arbitration controllers and method for high-speed CCD data storage - Google Patents
DDR3 arbitration controllers and method for high-speed CCD data storage Download PDFInfo
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Abstract
DDR3 arbitration controllers and method for high-speed CCD data storage.A kind of DDR3 arbitration controllers of the present invention, including Read-write Catrol module, DDR3 arbitration modules, IP kernel control module, data format dress mold changing block, read-write memory module.IP kernel control module is mainly responsible for driving read-write memory module, read-write memory module is correctly read and write data.Read-write memory module be responsible for front end to data flow and read-write memory module read or write speed matching, the read or write speed for reading and writing memory module is more many soon than the data flow needed for the data flow and subsequent conditioning circuit of front end, therefore the data that data write-in is read and write memory module and read from read-write memory module will carry out speeds match.Arbitration modules are responsible for, when multiple data flow applications are using read-write memory module, arbitrating the sequencing of application, determining response order, the use resource of distribution read-write memory module.Data format conversion module is responsible for being converted into the data format read from read-write memory module into the reference format needed for subsequent module.
Description
Technical field
The invention belongs to high-speed CCD image field of storage, particularly a kind of DDR3 for high-speed CCD data storage is arbitrated
Controller and method.
Background technology
In the video image of high-speed CCD is shown, some algorithms can use external memory storage, in the past external storage used
Device is all SRAM, because SRAM is easy to use, and current SRAM use technology is already close to maturation.It is used as CCD outside
Memory, SRAM current technologies can reach highest working frequency 167,000,000, and the storage that can not meet high-speed CCD will
Ask.SRAM can not be reduced, integrated level is low, it is impossible to meet again by the technology restriction of chip manufacturing in terms of volume simultaneously
Minimize CCD exploitation requirement.In addition, SRAM power consumption is larger, this is also the insurmountable problem of current technology, therefore SRAM
Low-power consumption CCD exploitation requirement can not be met.
The a variety of limitations used based on SRAM, the external memory storage of high-speed CCD has used SDRAM, first generation SDRAM and instead
Two generation DDR use single-ended clock signal, disturb larger when working frequency is high, with CCD external storages seldom.The third generation
DDR2 and forth generation DDR3 working frequencies are higher than first generation SDRAM and second generation DDR, therefore employ and can reduce the difference of interference
Clock signal is used as synchronised clock.DDR3 is very ripe in the memory techniques as notebook, because DDR3 operating rates are fast,
High speed storing is more suitable for, small volume is easy to integrated, the low reason of power consumption, and the external memory storage of high-speed CCD also begins to select
DDR3, but the interface configuration that DDR3 is used is complicated, CCD front ends to memory speed data stream and DDR3 read or write speed not
The reasons such as matching, will use DDR3 as external memory storage in the system of high-speed CCD, just have to solve interface configuration and speed
The problems such as degree matching.But good solution is there is no in the prior art.
The content of the invention
Technical problem solved by the invention is to provide a kind of DDR3 arbitration controllers for high-speed CCD data storage
And method.
The technical solution for realizing the object of the invention is：A kind of DDR3 for high-speed CCD data storage arbitrates control
Device, including Read-write Catrol module, DDR3 arbitration modules, IP kernel control module, data format conversion module and read-write memory module,
The Read-write Catrol module, DDR3 arbitration modules, IP kernel control module, read-write memory module are sequentially connected, wherein Read-write Catrol
Module is also connected with data format conversion module, and IP kernel control module and read-write memory module are also connected with Read-write Catrol module；
Read-write Catrol module receives data and the corresponding address write toward read-write memory module of extraneous input, and will be from
Read and write the corresponding address of data that memory module is read, Read-write Catrol module according to the threshold condition of setting by these three signals with
And read-write control signal is transferred to follow-up DDR3 arbitration modules；
DDR3 arbitrations control module decides whether to give IP kernel control module by these three signals, when DDR3 arbitrates control module
When determining these three signals to IP kernel control module, above three signal is transferred to read-write storage mould by IP kernel control module
Block, while the data of writing that will be stored in read-write memory module are write into read-write memory module in corresponding write address；Read address pair
Data in the read-write memory module answered pass IP kernel control module back from read-write memory module, and IP kernel control module is by the number of reading
According to read data enable be transferred to Read-write Catrol module, by Read-write Catrol module by the data of reading and read data enable export to
Data format conversion module, exports after Data Format Transform and is used to subsequent conditioning circuit.
The Read-write Catrol module includes address format conversion module, writes data format conversion module, the first Read-write Catrol
Module, the second Read-write Catrol module, write address fifo module, data fifo module is write, address fifo module is read, reads data FIFO
Module, the first time delay module, the second time delay module, signal feedback module, FIFO reset signals generation module and reading data format
Modular converter；
Address format modular converter, write the module for reading and writing of data format conversion module first and be connected, the first module for reading and writing and write
Address fifo module, write data fifo module, read address fifo module, signal feedback module be connected；Write address fifo module, write
Data fifo module and the first time delay module are connected；Read address fifo module and the second time delay module is connected；Write address FIFO moulds
Block, write data fifo module, read address fifo module be also connected with the second module for reading and writing；Signal feedback module and reading data FIFO
Module is connected；Read data fifo module and be connected with data format conversion module is read；FIFO reset signals generation module and write address
Fifo module, data fifo module is write, address fifo module is read, reads data fifo modules and be connected；
Address format modular converter and write the input of data format conversion module receiving front-end data flow write data and correspondingly
Write address, read address and from arbitration modules feed back can read-write control signal, by 4 continuous addresses and data difference
Be converted to an address and a data and export, while output has write enable signal, the marker data format turns
Change and finish, further work can be carried out, these signal outputs give the first Read-write Catrol module；First Read-write Catrol module will be write
Address, write data, read address signal be transferred to respectively write address fifo module, write data fifo module, read address fifo module,
FIFO write enable signals are transferred to above three fifo module by the first Read-write Catrol module simultaneously；Second Read-write Catrol module connects
Receive from write address fifo module and write the write address of data fifo module output and write data, the second Read-write Catrol module connects simultaneously
The signal for indicating data amount check in the two fifo modules is received, if write address fifo module and writing data in data fifo module
Number reaches high threshold, and the second Read-write Catrol module responds the write request of the first Read-write Catrol module, is otherwise not responding to；First prolongs
When module receive mark two fifo module whether read sky signal, then by mark two fifo module whether read sky signal connect
It is connected to write address fifo module and writes the reading Enable Pin of data fifo module, when reading spacing wave is non-NULL when being low level,
Read to enable effectively, high level is invalid；First Read-write Catrol module will read address and FIFO writes enable and is transferred to reading address FIFO moulds
Block, the second Read-write Catrol module receives the reading address read from address fifo module is read and mark reads number in the fifo module of address
According to the signal of number, if reading data amount check in the fifo module of address reaches high threshold, the second Read-write Catrol module response first
The read request of Read-write Catrol module；The signal whether mark reading address fifo module reads sky is transferred to reading by the second time delay module
The reading Enable Pin of address fifo module, reads to read to enable effectively when spacing wave is low level, high level is invalid；Read data FIFO
The data input pin of module receives the reading data being transmitted back to from IP kernel control module, and the Enable Pin of writing for reading data FIFO is received from IP
The reading data that nuclear control module transfer is returned, the first Read-write Catrol module receives the signal that mark reads data fifo module, allows read-write
Control module determines to respond read request, feedback module reception mark reading data according to the data amount check in the fifo module of address is read
Whether fifo module reads the signal of sky, the feedback request signal that the above-mentioned signal and the first Read-write Catrol module for whether reading sky is sent
Collective effect decides whether the data read-out for continuing to read in fifo module, if reading data fifo module has read sky, marks
Will reads whether data fifo module reads the signal of sky for high level, and by non-behind the door into low level, then no matter feedback signal is high
Level or low level, the FIFO reading enables for reading data fifo module are invalid, if mark reads whether data fifo module reads sky
Signal be low level, by it is non-behind the door turn into high level, be now judged as the feedback request that the first Read-write Catrol module is sent
Signal, if the signal high level, the FIFO for reading data fifo module is read to enable effectively, instead then invalid；Data format is read to turn
Change the mold block and receive the reading data for reading the reading of data fifo module, a data are converted into continuous four data, from reading data
The reading data that format converting module is exported are used to subsequent arbitration module；Reset signal generation module receiving front-end data flow is inputted
Frame signal, arbitration modules feed back to read-write requests signal, mark read data fifo module whether read sky signal, the module
The reset signal of generation supplies four fifo modules and used, to ensure that four fifo modules are all reset during each frame end.
The first time delay module and the second time delay module in the Read-write Catrol module include a NOT gate, two and door
With clock delay module, above-mentioned NOT gate is connected by one with door with clock delay module, clock delay module also with another
It is connected with door, another is output as the output of time delay module with door；
Clock delay module receives whether mark FIFO reads signal of the signal of sky by NOT gate with high level phase with after, when
Clock time delay module be delayed after a clock signal that exports again with high level phase with output result is as in Read-write Catrol module
The reading for reading data fifo module enables signal.
The data format conversion module includes data buffer storage fifo module and format converting module, data buffer storage FIFO moulds
Block, format converting module are sequentially connected, and data buffer storage fifo module receives from read-write memory module the data that read and right
The data output answered is enabled, format converting module receive the data exported from data buffer storage fifo module and front end data stream to
Frame signal, the data of format converting module final output are the picture signals of standard.
The read-write memory module uses DDR3 chips, model MT41J128M16-15E.
A kind of method based on above-mentioned DDR3 arbitration controllers, specifically includes following steps：
（1）Front end data stream will write the address read and write the data of memory module and write, read data
Address writes Read-write Catrol module, and Read-write Catrol module judges whether the data write reach threshold condition, when reaching threshold value bar
During part, Read-write Catrol module sends read-write requests to DDR3 arbitration modules；
（2）DDR3 arbitration modules are arbitrated according to the sequencing of multiple data flow applications, determine read-write memory module
Response order, when determine respond the data flow application when, DDR3 arbitration modules send read-write requests to IP kernel control module
Control；
（3）IP kernel control module responds the read-write requests of DDR3 arbitration modules, starts driving read-write memory module, by data
The corresponding address of write-in read-write memory module, or the data read-out that corresponding address in memory module will be read and write, input data lattice
Formula modular converter；
（4）The data read from read-write memory module are converted into the standard needed for subsequent module by data format conversion module
Form, and the row signal matched with standard image format and frame signal are produced, supply subsequent module is used.
Compared with prior art, its remarkable advantage is the present invention：1）The DDR3 arbitration controllers read or write speed of the present invention is fast,
The memory SRAM ratio read or write speeds made with conventional CCD are fast a lot, and SRAM read or write speeds only up to reach 167,000,000, DDR3
Chip can reach hundreds of million.2）DDR3 chip volumes are more much smaller than SRAM, and integrated level is high, has saved design space.3）
DDR3 chip power-consumptions are lower than SRAM, can mitigate the operating pressure of power panel in CCD systems.4）The DDR3 arbitration controls of the present invention
Device can realize that DDR3 chips are used alternatingly in multiple data flows.5）DDR3 chips are using interface and configure more complicated than SRAM a lot,
Restrictive condition is more, but the present invention is simple to the use interface of user, and restrictive condition is few, the use of interface almost with SRAM mono-
Cause.
The present invention is described in further detail below in conjunction with the accompanying drawings.
Brief description of the drawings
Fig. 1 is the basic flow sheet of Read-write Catrol module.
Fig. 2 is the time delay module structural representation in Fig. 1.
Fig. 3 is the structure chart of data format conversion module.
Fig. 4 is the complete external interface figure of DDR3 arbitration controllers.
Fig. 5 is the DDR3 arbitration controller structure charts of the present invention.
Fig. 6 is the pin interface figure of IP kernel control module.
Fig. 7 is the data stream format figure of specific embodiment of the invention read-write.
Embodiment
A kind of DDR3 arbitration controllers of the present invention, including Read-write Catrol module, DDR3 arbitration modules, IP kernel control mould
Block, data format dress mold changing block, read-write memory module.IP kernel control module is mainly responsible for driving read-write memory module, makes read-write
Memory module can correctly read and write data.Read-write memory module is mainly responsible for the data flow given front end and read-write memory module read-write
Speeds match problem, the read or write speed of read-write memory module is up to hundreds of million, and the data flow of front end does not reach this speed, subsequently
Module also without so fast speed, therefore data write-in read-write memory module and the number that is read from read-write memory module
According to speeds match will be carried out.Arbitration modules are mainly responsible for when multiple data flow applications are using read-write memory module, to application
Sequencing arbitrated, determine first to respond the application of which data flow, the use resource of distribution read-write memory module.Data
Format converting module is mainly responsible for being converted into the data format read from read-write memory module into the standard needed for subsequent module
Form.
The present invention is further elaborated below in conjunction with the accompanying drawings.
With reference to Fig. 1, the Read-write Catrol module that the present invention is invented for the DDR3 arbitration controllers of high-speed CCD data storage,
Including address format conversion module, write data format conversion module, the first Read-write Catrol module, the second Read-write Catrol module, write
Address fifo module, data fifo module is write, address fifo module is read, reads data fifo modules, the first time delay module, second prolongs
When module, signal feedback module, FIFO reset signals generation module, read data format conversion module.
Address format conversion module is by continuous 4 addresses of input and data conversion with data format conversion module is write
For an address and data, therefore the address given for leading portion data flow and the number of data a line must be 4 integral multiples.Read
Data format conversion module is that a data are changed into 4 continuous data in address.The number of the data a line therefore exported
It is also 4 integral multiple, therefore combines Fig. 5, the data exported from DDR3 will be converted into the data lattice of standard by data format
Formula could supply subsequent module and use.
When needing to write data, algorithm basic module is ceaselessly intended to the address write and data are sent to write address FIFO and
Write data FIFO；When the quantity for writing data FIFO and write address FIFO exceedes the high threshold of setting（The threshold value is carried out as needed
Setting, such as 512 bytes）When, start to DDR3 arbitration controller applications to write address FIFO and write data FIFO progress reading behaviour
Make, the data write in data FIFO are write into corresponding address in DDR3, when Low threshold of the write address FIFO quantity less than setting
（The threshold value is set as needed, such as 256 bytes）When stop to the application of DDR3 arbitration controllers to write address FIFO and
Write data FIFO read operation；To having been written into the address counting number in write address FIFO in algorithm basic module, when fast
During a full frame number, provide one and write frame end signal wf_end（After second from the bottom time is read stop signal, last time is read to stop
High level is provided before stop signal, last time reads zero setting after stop signal）To arbitration controller, the signal shielding last
Secondary reading stop signal, enables arbitration modules to read address and data in two FIFO respectively always, until two FIFO are
It is empty（FIFO empty signals can be linked into arbitration modules and monitor whether FIFO is empty）When stop read operation, now complete
The address of one whole two field picture and data read operation, DDR3 is written with by entire image.
, it is necessary to which the address for wanting the data read is stored in into reading ground before algorithm needs to read the data of some storage space
Location FIFO, algorithm basic module will read address write-in under the control of read control signal, ceaselessly and read in the FIFO of address；When reading ground
When location FIFO storage space is more than the high threshold set（The threshold value is set as needed, such as 896 bytes）, to
DDR3 arbitration controller applications start to carry out read operation to reading address FIFO, and the data that corresponding address is read from DDR3 are written to
Read in data FIFO.When reading address FIFO storage space less than the Low threshold set（The threshold value is set as needed
It is fixed, such as 768 bytes）, the read operation to reading address FIFO is stopped to the application of DDR3 arbitration controllers；In algorithm basic module
To having been written into the address counting number read in the FIFO of address, when a completely frame number soon, provide one and read frame end signal rf_
end（After second from the bottom time is read stop signal, last time is read to provide high level before stop signal, and last time is read to stop
Zero setting after signal）To arbitration controller, signal shielding last time reads address FIFO reading stop signal, makes arbitration modules
The address in the FIFO of address can be read respectively always, until it is sky（The empty signals for reading address FIFO can be linked into
Whether it is empty that it is monitored in arbitration modules）.Reading data FIFO is then：If read data data fifo more than the high threshold set
（Such as 768 bytes）, the data in data FIFO are continuously read by algorithm basic module, and it is counted, work as reading
Stop reading during enough frames.Make the blanking time of interframe identical by FIFO buffering.
All FIFO need to empty after the completion of read-write operation.The data output exported from Read-write Catrol module enables signal
The data syn-chronization for being and being exported from data FIFO is read, when data are from when reading data FIFO outputs, data output is enabled and just put
For high level, otherwise it is set to low level.
With reference to Fig. 2, the Read-write Catrol module that the present invention is invented for the DDR3 arbitration controllers of high-speed CCD data storage,
Whether mark FIFO reads the signal of sky by signal output with after of NOT gate and high level phase to time delay module, and time delay module is delayed
The signal exported after one clock is want to enable signal as FIFO reading with, output result again with high level.
With reference to Fig. 3, the Data Format Transform mould that the present invention is invented for the DDR3 arbitration controllers of high-speed CCD data storage
Block, including data buffer storage fifo module, format converting module.When it is high level that data output, which is enabled, represent that DDR3 is begun with
Data read-out, caches 3 rows, the data read from FIFO and front end from the DDR3 data read in data buffer storage fifo module
The frame signal that data flow is given（The beginning of mark one two field picture）Pattern of the input modular converter, finally exports the mark needed for subsequent module
Quasi- data format, row signal（Sign image a line starts）, frame signal.
It is that single data flow application uses DDR3 signal connection structures, including Read-write Catrol module, arbitration mould with reference to Fig. 5
Block, IP kernel control module, data format conversion module, front end data stream will write the data and corresponding address toward DDR3, with
And to read the corresponding address of data and write in Read-write Catrol module, Read-write Catrol module decides whether this according to threshold condition
Three signals and read-write control signal give subsequent arbitration module, are decided whether to control these three signals to DDR3 by arbitration modules
Device IP kernel processed.When arbitration modules determine will three signals to controller IP kernel when, DDR3 controllers IP kernel ability these three are believed
Number it is transferred to DDR3 chips.The data of writing for being stored in DDR3 have just write into corresponding write address in DDR3.Read address corresponding
Data in DDR3 pass DDR3 controller IP kernels back from DDR3 chips, and the data of reading and reading data are enabled and are transferred to reading by IP kernel
Control module is write, is exported to data format conversion module, is exported after Data Format Transform to follow-up by Read-write Catrol module
Circuit is used.
Data flow 1 is labeled as ' 01 ', data flow 2 is labeled as by the course of work of arbitration modules by taking two data streams as an example
' 10 ', when two algorithms are not applied, current state is labeled as ' 00 ', and when data flow 1 is applied, current state is labeled as
' 01 ', when data flow 1 has also been not carried out, if now data flow 2 also applies using DDR3, DDR3 continues respective counts this moment
According to the application of stream 1, and data flow 2 is come in application troop.' 10 ' are designated as after data flow 1 has been performed, then by current markers,
Perform data flow 2.If when data flow 1 and data flow 2 are applied simultaneously, according to order, the Shen of DDR3 elder generations response traffic 1
Please, the application of response traffic 2 again after having performed.
In the case of single data flow application, arbitration modules do not play a role in fact, only multiple data flow applications
Substantial role can be just played using arbitration modules during DDR3.
With reference to Fig. 6, the pin interface figure of IP kernel control module, IP kernel control module is to generate soft core by quartus, generation
Step：
TOOLS->MegaWizard Plug-In Manager.The setting of IP kernel is according to DDR3 model, with reference to the DDR3
The datasheet selection parameters configuration of chip.After parameter configuration is complete, point Finish clicks on Generate afterwards.Needed after generation IP kernel
The pin of module is configured, part pin is defined as follows：
（1）The pin of mem beginnings is directly to be connected with DDR3 chips, it is not necessary to configured.
（2）Pll_ref_clk is the reference clock of IP kernel, is different from afi_clk and afi_half_clk, afi_clk and
Afi_half_clk is the clock that DDR3 reads data, and which clock to read data with needs to set when IP kernel is generated.
（3）Global_reset_n and soft_reset_n are reset signals, are typically all set to high level.
（4）Avl_ready, which is similar to, enables signal, is that DDR3 tells user to be already prepared to start to read and write data.
（5）Avl_rdata_valid is to read useful signal, and effectively, the signal is the data read when being high level
Used as the Enable Pin of DDR3 data outputs to data format conversion module.
（6）Avl_be is that position enables signal, is typically set to 1.
（7）Avl_size is the data amount check once read and write.
（8）Avl_addr, avl_wdata, avl_write_req are write address respectively, write data, write enable.
（9）Avl_rdata and avl_read_req are to read data and read to enable respectively.
（10）Local_init_done, local_cal_success, local_cal_fail are DDR3 initialization flags
Signal, when local_init_done, local_cal_success are high level, local_cal_fail is low level, then
DDR3 is initialized successfully, is otherwise initialized unsuccessful.
（11）Oct_rzqin is DDR3 impedance matching pin, it is necessary to be connected with FPGA some pin.
After pin configuration is good, first compile, can be reported an error when compiling proceeds to Fitter (Place＆Route), when being reported an error
When being more than 700 identical mistake by mistake, then need the program of the automatic distribution pin of operation one, step：Tools->Tcl
Scripts->Pin assignment, are then compiled again, could be compiled successfully.Found by experimental debugging, it is necessary to according to this
Two step sequencings could compile passing through.
With reference to Fig. 4, it is the complete external interface schematic diagram of the present invention, comes to the interface with 5 data flows, each algorithm
Interface include write clock, write enables, write data, write address, read enable, read address, reading data, application method is as RAM.
One group of output interface of each algorithm correspondence, is field signal, row signal, data output respectively.
With reference to Fig. 7, specific embodiment of the invention：The present invention is quartus12.1 using software, and the FPGA used is
Cyclone V, the DDR3 chip models used is MT41J128M16-15E, the data format as shown 7 that CCD is used.The data
Form often go before have 236 invalid datas, behind also have 426 invalid datas, only in the middle of is 1920 valid data, be
The address for meeting write-in data is continuous 4 integral multiple, and often capable valid data are only write when writing data into DDR3 i.e.
1920*1150, transmission of data form such as Fig. 7 after data format is converted, is 2583*1150, often capable above 236 invalid numbers
According to, behind also have 426 invalid datas.CCD front ends output data flow be four circuit-switched datas, by this circuit-switched data be combined into one it is complete
Whole image needs to use DDR3 storages.Four circuit-switched datas two paths of data is combined into first by RAM, i.e., upper half images and lower half
The valid data of this two images signal have been stored to the corresponding addresses of DDR3 by width image respectively, then defeated complete figure all the way
As signal, the picture signal only includes the valid data of often row signal, and the picture signal can after data format conversion module
To obtain the reference format shown in Fig. 7.
Claims (5)
1. a kind of DDR3 arbitration controllers for high-speed CCD data storage, it is characterised in that including Read-write Catrol module,
DDR3 arbitration modules, IP kernel control module, data format conversion module and read-write memory module, the Read-write Catrol module,
DDR3 arbitration modules, IP kernel control module, read-write memory module are sequentially connected, and wherein Read-write Catrol module also turns with data format
Change the mold block to be connected, IP kernel control module and read-write memory module are also connected with Read-write Catrol module；
Read-write Catrol module receives data and the corresponding address write toward read-write memory module of extraneous input, and will be from read-write
The corresponding address of data that memory module is read, Read-write Catrol module is according to the threshold condition of setting by these three signals and reading
Write control signal is transferred to follow-up DDR3 arbitration modules；
DDR3 arbitrations control module decides whether to give IP kernel control module by these three signals, when DDR3 arbitration control modules are determined
During by these three signals to IP kernel control module, above three signal is transferred to read-write memory module by IP kernel control module, together
When will be stored in the data of writing of read-write memory module and write into read-write memory module in corresponding write address；Read the corresponding reading in address
Write data in memory module and pass IP kernel control module back from read-write memory module, IP kernel control module is by the data of reading and reading
Data enable and are transferred to Read-write Catrol module, and the data of reading and reading data are enabled into output by Read-write Catrol module gives data lattice
Formula modular converter, exports after Data Format Transform and is used to subsequent conditioning circuit；
The Read-write Catrol module include address format conversion module, write data format conversion module, the first Read-write Catrol module,
Second Read-write Catrol module, write address fifo module, write data fifo module, read address fifo module, read data fifo modules,
First time delay module, the second time delay module, signal feedback module, FIFO reset signals generation module and reading data format modulus of conversion
Block；
Address format modular converter, write data format conversion module and be connected respectively with the first module for reading and writing, the first module for reading and writing and
Write address fifo module, write data fifo module, read address fifo module, signal feedback module be connected；Write address fifo module,
Write data fifo module and the first time delay module is connected；Read address fifo module and the second time delay module is connected；Write address FIFO
Module, write data fifo module, read address fifo module be also connected with the second module for reading and writing；Signal feedback module and reading data
Fifo module is connected；Read data fifo module and be connected with data format conversion module is read；FIFO reset signals generation module and write
Address fifo module, data fifo module is write, address fifo module is read, reads data fifo modules and be connected；
Address format modular converter and write writing data and corresponding writing for data format conversion module receiving front-end data flow input
Address, the read-write control signal read address and meeting is fed back from arbitration modules, 4 continuous addresses and data are changed respectively
For an address and a data and export, while output has write enable signal, the marker Data Format Transform is complete
Finish, further work can be carried out, these signal outputs give the first Read-write Catrol module；First Read-write Catrol module will write ground
Location, write data, read address signal be transferred to respectively write address fifo module, write data fifo module, read address fifo module,
FIFO write enable signals are transferred to above three fifo module by the first Read-write Catrol module simultaneously；Second Read-write Catrol module connects
Receive from write address fifo module and write the write address of data fifo module output and write data, the second Read-write Catrol module connects simultaneously
The signal for indicating data amount check in the two fifo modules is received, if write address fifo module and writing data in data fifo module
Number reaches high threshold, and the second Read-write Catrol module responds the write request of the first Read-write Catrol module, is otherwise not responding to；First prolongs
When module receive mark two fifo module whether read sky signal, then by mark two fifo module whether read sky signal connect
It is connected to write address fifo module and writes the reading Enable Pin of data fifo module, when reading spacing wave is non-NULL when being low level,
Read to enable effectively, high level is invalid；First Read-write Catrol module will read address and FIFO writes enable and is transferred to reading address FIFO moulds
Block, the second Read-write Catrol module receives the reading address read from address fifo module is read and mark reads number in the fifo module of address
According to the signal of number, if reading data amount check in the fifo module of address reaches high threshold, the second Read-write Catrol module response first
The read request of Read-write Catrol module；The signal whether mark reading address fifo module reads sky is transferred to reading by the second time delay module
The reading Enable Pin of address fifo module, reads to read to enable effectively when spacing wave is low level, high level is invalid；Read data FIFO
The data input pin of module receives the reading data being transmitted back to from IP kernel control module, and the Enable Pin of writing for reading data FIFO is received from IP
The reading data that nuclear control module transfer is returned, the first Read-write Catrol module receives the signal that mark reads data fifo module, allows read-write
Control module determines to respond read request, feedback module reception mark reading data according to the data amount check in the fifo module of address is read
Whether fifo module reads the signal of sky, the feedback request signal that the above-mentioned signal and the first Read-write Catrol module for whether reading sky is sent
Collective effect decides whether the data read-out for continuing to read in fifo module, if reading data fifo module has read sky, marks
Will reads whether data fifo module reads the signal of sky for high level, and by non-behind the door into low level, then no matter feedback signal is high
Level or low level, the FIFO reading enables for reading data fifo module are invalid, if mark reads whether data fifo module reads sky
Signal be low level, by it is non-behind the door turn into high level, be now judged as the feedback request that the first Read-write Catrol module is sent
Signal, if the signal high level, the FIFO for reading data fifo module is read to enable effectively, instead then invalid；Data format is read to turn
Change the mold block and receive the reading data for reading the reading of data fifo module, a data are converted into continuous four data, from reading data
The reading data that format converting module is exported are used to subsequent arbitration module；Reset signal generation module receiving front-end data flow is inputted
Frame signal, arbitration modules feed back to read-write requests signal, mark read data fifo module whether read sky signal, the module
The reset signal of generation supplies four fifo modules and used, to ensure that four fifo modules are all reset during each frame end.
2. the DDR3 arbitration controllers according to claim 1 for high-speed CCD data storage, it is characterised in that described
The first time delay module and the second time delay module in Read-write Catrol module include a NOT gate, two and door and clock delay mould
Block, above-mentioned NOT gate is connected by one with door with clock delay module, and clock delay module is also connected with another with door, separately
One time delay module is output as with door output；
Clock delay module receives whether mark FIFO reads signal of the signal of sky by NOT gate with high level phase with after, and clock prolongs
When module be delayed after a clock signal that exports again with high level phase with output result is used as reading in Read-write Catrol module
Signal is enabled according to the reading of fifo module.
3. the DDR3 arbitration controllers according to claim 1 for high-speed CCD data storage, it is characterised in that described
Data format conversion module includes data buffer storage fifo module and format converting module, data buffer storage fifo module, form conversion
Module is sequentially connected, and data buffer storage fifo module receives the data and corresponding data output read from read-write memory module
Enable, format converting module receive the data that are exported from data buffer storage fifo module and front end data stream to frame signal, lattice
The data of formula modular converter final output are the picture signals of standard.
4. the DDR3 arbitration controllers according to claim 1 for high-speed CCD data storage, it is characterised in that described
Read and write memory module and use DDR3 chips, model MT41J128M16-15E.
5. a kind of processing method based on DDR3 arbitration controllers described in claim 1, it is characterised in that comprise the following steps：
(1) front end data stream will write the address read and write the data of memory module and write, read the address of data
Read-write Catrol module is write, Read-write Catrol module judges whether the data of write-in reach threshold condition, when threshold conditions are reached,
Read-write Catrol module sends read-write requests to DDR3 arbitration modules；
(2) DDR3 arbitration modules are arbitrated according to the sequencing of multiple data flow applications, determine the sound of read-write memory module
Should sequentially, when determining to respond the application of the data flow, DDR3 arbitration modules send read-write requests control to IP kernel control module；
(3) IP kernel control module responds the read-write requests of DDR3 arbitration modules, starts driving read-write memory module, writes data into
The corresponding address of memory module, or the data read-out that corresponding address in memory module will be read and write are read and write, input data form turns
Change the mold block；
(4) data read from read-write memory module are converted into the reticle needed for subsequent module by data format conversion module
Formula, and the row signal matched with standard image format and frame signal are produced, supply subsequent module is used.
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| CN108897511B (en) * | 2018-07-05 | 2021-03-05 | 四川长九光电科技有限责任公司 | Method for receiving and displaying images with different frame frequencies |
| CN109062538B (en) * | 2018-07-10 | 2020-11-20 | 豪威科技(上海)有限公司 | Circular first-in first-out buffer and data transmission interface, system and method |
| CN109766285A (en) * | 2019-01-10 | 2019-05-17 | 中国科学院长春光学精密机械与物理研究所 | A kind of the SDRAM access control system and control method of burst mode |
| CN112732603A (en) * | 2019-10-14 | 2021-04-30 | 广州飒特红外股份有限公司 | Multi-channel VDMA control method and application thereof |
| CN111581132B (en) * | 2020-04-27 | 2022-03-25 | 武汉中科牛津波谱技术有限公司 | Extensible multiport DDR3 controller based on FPGA |
| CN111722827B (en) * | 2020-05-28 | 2022-07-15 | 江苏方天电力技术有限公司 | Efficient DDR access method |
| CN111949577B (en) * | 2020-07-30 | 2023-03-14 | 电子科技大学 | High-speed high-precision sampling data large-capacity storage and rapid transmission method |
| CN112052206B (en) * | 2020-08-31 | 2023-03-28 | 浙江双成电气有限公司 | Multi-port data storage system based on arbitration |
| CN112241390B (en) * | 2020-10-22 | 2022-08-30 | 上海兆芯集成电路有限公司 | Host interconnection apparatus and method thereof |
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