CN113051195A - Memory, GPU and electronic equipment - Google Patents
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Abstract
The embodiment of the application provides a memory, a GPU and an electronic device, wherein the memory comprises a plurality of protocol conversion units, a channel management unit and a plurality of RAM memory banks: the protocol conversion units are used for receiving access requests sent by a plurality of access request sources, performing protocol conversion on the access requests and sending the access requests to the channel management unit; the channel management unit is used for allocating an arbitration management interface to each access request according to a preset sequence and accessing the RAM memory bank after arbitration is passed, the RAM memory bank is in one-to-one connection with the arbitration management interface, and the preset sequence is the sequence of receiving the access requests. A plurality of RAM memory banks are integrated in one memory, and a corresponding channel management unit and a protocol conversion unit are arranged to process a plurality of received access requests, so that the requirement of a plurality of access sources for accessing the memory is met.
Description
Technical Field
The present application relates to the field of memory access technologies, and in particular, to a memory, a GPU, and an electronic device.
Background
A Graphics Processing Unit (GPU) is a microprocessor specially used for Processing images or Graphics, and is applied to a display system of an electronic terminal to reduce the pressure of a Central Processing Unit (CPU) in image or Graphics Processing.
A Random Access Memory (RAM) and a plurality of operation units are arranged in the GPU, and each operation unit can be used as an Access source to Access the RAM. When data processing is carried out, a plurality of access sources need to be satisfied to access the RAM, and most of the RAMs only support one or two access sources to access the RAM, so that the requirement that the plurality of access sources access the memory is difficult to satisfy.
Disclosure of Invention
The embodiment of the application provides a memory, a GPU and an electronic device, and can effectively solve the problem that the requirement that a plurality of access sources access the memory is difficult to meet.
According to a first aspect of embodiments of the present application, there is provided a memory, the memory including a plurality of protocol conversion units, a channel management unit, and a plurality of RAM banks; the protocol conversion units are used for receiving access requests sent by a plurality of access request sources, performing protocol conversion on the access requests and sending the access requests to the channel management unit; the channel management unit is used for allocating an arbitration management interface to each access request according to a preset sequence and accessing the RAM memory bank after arbitration is passed, the RAM memory bank is in one-to-one connection with the arbitration management interface, and the preset sequence is the sequence of receiving the access requests.
According to a second aspect of the embodiments of the present application, there is provided a graphics processor, which includes a plurality of arithmetic units and the memory provided in the first aspect.
According to a third aspect of embodiments of the present application, there is provided an electronic device including the graphics processor provided in the second aspect.
The memory provided by the embodiment of the application comprises a plurality of protocol conversion units, and a channel management unit comprises a plurality of RAM memory banks; the protocol conversion units are used for receiving access requests sent by a plurality of access request sources, performing protocol conversion on the access requests and sending the access requests to the channel management unit; the channel management unit is used for allocating an arbitration management interface to each access request according to a preset sequence and accessing the RAM memory bank after arbitration is passed, the RAM memory bank is in one-to-one connection with the arbitration management interface, and the preset sequence is the sequence of receiving the access requests. A plurality of RAM memory banks are integrated into a memory, and a corresponding channel management unit and a protocol conversion unit are arranged to process a plurality of received access requests, so that the requirement of a plurality of access sources for accessing the memory is met.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application. In the drawings:
FIG. 1 is a block diagram of a memory according to an embodiment of the present disclosure;
fig. 2 is a block diagram of a protocol conversion unit according to an embodiment of the present application;
fig. 3 is a block diagram of a channel management unit according to an embodiment of the present application;
FIG. 4 is a schematic diagram of a connection providing multiple address partitioning units and multiple arbitration management, according to an embodiment of the present application;
FIG. 5 is a block diagram of a GPU according to an embodiment of the present disclosure;
FIG. 6 is a flow chart of a method for memory access provided by one embodiment of the present application;
fig. 7 is a block diagram of an electronic device according to an embodiment of the present application.
Detailed Description
A Graphics Processing Unit (GPU) is a microprocessor specially used for Processing images or Graphics, and is applied to a display system of an electronic terminal to reduce the pressure of a Central Processing Unit (CPU) in image or Graphics Processing.
A Random Access Memory (RAM) and a plurality of operation units are arranged in the GPU, and each operation unit can be used as an Access source to Access the RAM. When a RAM access is made, most of the RAM can be accessed by only one access source. However, when a chip performs data processing, it is generally necessary to satisfy access to the RAM by a plurality of access sources, and it is difficult to satisfy multiple accesses to the RAM.
The inventors have discovered in their research that only one or two access sources are typically supported in RAM internal to the GPU to access the RAM. Then, in data processing inside the GPU, there is often a case where a plurality of access sources simultaneously access the RAM. The RAM supporting one or two access sources can be combined together to form a large memory, and corresponding units are correspondingly arranged to process access requests sent by a plurality of access sources, so that the RAM can be accessed in multiple ways.
Therefore, the embodiment of the present application provides a memory, where the memory includes a plurality of protocol conversion units, a channel management unit and a plurality of RAM banks; the protocol conversion units are used for receiving access requests sent by a plurality of access request sources, performing protocol conversion on the access requests and sending the access requests to the channel management unit; the channel management unit is used for allocating an arbitration management interface to each access request according to a preset sequence and accessing the RAM memory bank after arbitration is passed, the RAM memory bank is in one-to-one connection with the arbitration management interface, and the preset sequence is the sequence of receiving the access requests. A plurality of RAM memory banks are integrated into a memory, and a corresponding channel management unit and a protocol conversion unit are arranged to process a plurality of received access requests, so that the requirement of a plurality of access sources for accessing the memory is met. The multi-access memory can not only accelerate the efficiency of data access, but also realize data sharing, so that a plurality of access request sources can read and write the memory, and the data processing is more facilitated.
In order to make the technical solutions and advantages of the embodiments of the present application more apparent, the following further detailed description of the exemplary embodiments of the present application with reference to the accompanying drawings makes it clear that the described embodiments are only a part of the embodiments of the present application, and are not exhaustive of all embodiments. It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict.
Referring to fig. 1, a block diagram of a memory provided in the present application is shown. The memory (Random100 includes a plurality of protocol conversion units 10, a channel management unit 20, and a plurality of RAM banks 30.
The protocol conversion unit 10 is configured to receive access requests sent by multiple access request sources, perform protocol conversion on the access requests, and send the access requests to the channel management unit, so as to mainly complete conversion between an external access protocol and an internal data transmission protocol. That is, the protocol conversion unit 10 may receive an access request sent by an access request source based on an external access protocol, convert the access request into data corresponding to an internal data transmission protocol after receiving the access request, and send the access request subjected to protocol conversion to the channel management unit 20.
The external access protocol may be configured as an Advanced eXtensible Interface (AXI) Bus or an Advanced High Performance Bus (AHB) Bus Interface as needed. The internal data transmission protocol can also be configured according to actual needs.
Referring to fig. 2, a block diagram of a protocol conversion unit according to an embodiment of the present application is shown. The protocol conversion unit 10 includes a write data management subunit 11, a read data management subunit 12, and a read-write order management subunit 13.
The access request sent by the access request source may be a read data request or a write data request. When the access request is a write data request, the write data management subunit 11 receives write data corresponding to the write data request, converts the write data request into a write data transmission request carrying the write data when the write data is received, and sends the write data transmission request to the channel management unit 20 through an internal data transmission interface, so as to instruct the channel management unit 20 to process the write data transmission request. The data writing request is received based on an external protocol, and the data writing transmission request is obtained based on conversion of the internal data transmission protocol.
When the access request is a read data request, the read data management subunit 12 converts the read data request into a read data transmission request when receiving the read data request, and sends the read data transmission request to the channel management unit 20 through the internal data transmission interface, so as to instruct the channel management unit 20 to process the read data transmission request.
The read-write sequence management unit 13 is configured to control the read data management subunit and the write data management subunit, and send the write data transmission request and the read data transmission request according to a preset sequence. Wherein the preset sequence is the sequence of receiving the access requests.
For example, four access requests, namely a read data request a, a write data request B, a read data request C, and a write data request D, are received in sequence. The write data management subunit 11 receives the write data request B and the write data request D in sequence. The read data pipe unit 12 receives a read data request a, a read data request C in turn. After the data writing management subunit 11 and the data reading management subunit perform protocol conversion, a data reading transmission request a, a data writing transmission request B, a data reading transmission request C, and a data writing transmission request D are obtained. The read-write sequence control subunit 13 may control the read data management subunit 12 to send the read data transmission request a first, then control the write data management subunit 11 to send the write data transmission request B, then control the read data management subunit 12 to send the read data transmission request C, and finally control the write data management subunit 11 to send the write data transmission request D.
The read-write order management subunit 13 can realize maximum utilization of the bandwidth of the RAM, ensure that read-write is executed according to the order, and avoid read-write errors.
It can be understood that, when the access request is a read data request, corresponding read data needs to be returned, so that the read data management subunit 12 can receive the corresponding read data through the channel management unit 20 and send the read data to a corresponding access request source.
Meanwhile, for the read data requests of a plurality of continuous different addresses, the channel management unit 20 cannot guarantee the order of the returned read data. That is, the issued read data request has access conflict with other access requests, and multiple simultaneous accesses to the same RAM bank 30 occur, resulting in congestion. This situation may be understood as an access conflict, in which case a subsequently issued read data transfer request may return read data a step before.
For example, write data request a accesses RAM bank (0), read data request B accesses RAM bank (0), and write data request C accesses RAM bank (1), in that order write data request a, read data request B, and write data request C. At this time, since both the write data request a and the read data request B access the RAM bank (0), data needs to be written first and then read. While write data request C may directly access RAM bank (1), possibly returning read data first. And the corresponding read data of the read data request B is returned.
Therefore, the read-write order management subunit 13 is further configured to control the read-write order management subunit to send the received read data to the access request source sending the read data request according to a first order, where the first order is an order in which the read-write order management subunit receives the read data requests.
As described in the foregoing example, the read data management subunit receives the read data C corresponding to the read data request C first and then receives the read data B corresponding to the read data request B, and the read/write order management subunit 13 may record the first order, that is, the order of receiving the read data requests is to read the read data request B first and then to read the data request C, so that the read data management subunit 12 may be controlled to send the read data B first and then to send the read data C to the corresponding access request source.
For another example, if the access request sent by the access request source (0) is a read data request, the read data is sent to the access request source (0) when the read/write order management subunit 13 receives the returned read data.
The protocol conversion unit 10 performs protocol conversion on the received access request and then sends the access request to the channel management unit 20. The channel management unit 20 may thus allocate a corresponding arbitration management interface to the received write data transmission request or read data transmission request, and send the write data transmission request or read data transmission request to the RAM bank through the arbitration management interface.
Referring to fig. 3, a block diagram of the channel management unit 20 is shown. The channel management unit 20 includes a plurality of address division sub-units 21, a multi-master-multi-slave arbitration management sub-unit 22, and a read-write consistency management sub-unit 23.
The address dividing subunit 21 is configured to allocate multiple masters to multiple slaves arbitration management subunits according to access addresses carried in the write data transmission request or the read data transmission request. The access addresses may be allocated according to an address division principle, which may be set according to actual needs, for example, the addresses may be divided into multiple segments according to a fixed address division, and each segment is sequentially sent to the corresponding arbitration management interface.
The multi-master-to-multi-slave arbitration management subunit 22 includes a plurality of arbitration management interfaces 221, where each arbitration management interface 221 is configured to send the write data transmission request or the read data transmission request to the corresponding RAM bank 30 by using a first-in-first-out queue. That is, the multi-master-to-multi-slave arbitration management subunit 22 is implemented by using a many-to-one arbitration logic, and includes a plurality of arbitration management interfaces 221, and when receiving a write data transmission request or a read data transmission request sent by the address division subunit 21, each write data transmission request or read data transmission request may be sent to each arbitration management interface 221. Referring now to FIG. 4, a schematic diagram of the connection of a plurality of address partitioning units and a plurality of arbitration management interfaces is shown.
Each arbitration management interface 221 uses a first-in first-out queue to sequence each write data transmission request or read data request, and sequentially transmits the data transmission request or read data request to a corresponding RAM bank.
The read-write consistency management subunit 23 is configured to control the multiple arbitration management interfaces 221 to send the write data transmission request or the read data transmission request to the corresponding RAM banks 30 according to the preset sequence. The read-write consistency management subunit 23 is a global management subunit, and can record the sequence, i.e., a preset sequence, of the write data transmission request or the read data transmission request received from the protocol conversion unit 10. And controlling the order of sending the read data transmission requests or the write data transmission requests to the arbitration management interface 221 according to the preset order, and ensuring that the access requests sent by each access request source are executed according to the order.
And if a data reading request is received firstly and a data writing request is received to access the same RAM memory bank, reading the data in the RMA memory bank firstly and then writing the data into the RAM memory bank. And if the data writing request is received firstly and the data reading request is received secondly, firstly writing the data into the RAM memory bank and then reading the data in the RAM memory bank.
When receiving a read data transmission request sent by the arbitration management interface 221, the RAM memory bank 30 reads data to obtain read data, returns the read data to the channel management unit 20, sends the read data to the protocol conversion unit 10 by the channel management unit 20, and sends the read data to a corresponding access request source by the protocol conversion unit 10.
When the RAM bank 30 receives a write data transfer request sent by the arbitration management interface 221, the write data in the write data transfer request may be written into the RAM bank 30.
The memory comprises a plurality of address division subunits, arbitration management interfaces and protocol conversion units, wherein the number of the address division subunits, the arbitration management interfaces and the number of the protocol conversion units are the same. In the embodiment of the application, the system can be 8 protocol conversion units, 8 address dividing sub-units and 8 arbitration management interfaces, and supports simultaneous access of 8 access requests. It is understood that the specific number can be set according to actual needs, and is not limited specifically herein.
Fig. 5 is a block diagram of a GPU according to an embodiment of the present disclosure. As shown in fig. 5, the present embodiment provides a GPU300, which includes: a plurality of arithmetic units 200 and a memory 100, wherein the plurality of arithmetic units 200 can be used as access sources to access the memory 100. The memory 100 may employ any of the various embodiments described above.
Referring to fig. 6, an embodiment of the present application provides a memory access method, which may specifically include the following steps.
Step 110, a plurality of protocol conversion units receive access requests sent by a plurality of access request sources, and send the access requests to a channel management unit after performing protocol conversion on the access requests.
And step 120, the channel management unit allocates an arbitration management interface for each access request according to a preset sequence, and accesses a RAM memory bank after arbitration is passed, wherein the RAM memory bank is connected with the arbitration management interface in a one-to-one manner.
The multiple access request sources can send access requests to the protocol conversion unit, and the protocol conversion unit carries out protocol conversion on the access requests and then sends the access requests to the channel management unit through the internal data transmission interface. The access request may be a read data request or a write data request, and the protocol conversion unit converts the read data request into a read data transmission request and converts the write data request into a write data transmission request, where the write data transmission request includes write data, that is, data to be written into the RAM bank. And the protocol conversion unit forwards the corresponding write data transmission request and read data transmission request to the channel management unit according to the sequence of receiving the access requests, namely the preset sequence.
Thus, the channel management unit may receive the read data transmission request or the write data transmission request, and allocate an arbitration management interface to each read data transmission request or write data transmission request according to a preset sequence.
The arbitration management interface is connected with the RAM memory bank in a one-to-one mode, and when receiving a read data transmission request or a write data transmission request, the arbitration management interface sends the read data transmission request or the write data transmission request to the RAM memory bank in a first-in first-out queue. So that the RAM banks can read or write data. The rest of the contents may be referred to the description of the foregoing embodiments, and are not repeated herein to avoid redundancy.
A plurality of RAM memory banks supporting one access source are integrated into one memory, multiple access request sources can be supported to access simultaneously, corresponding protocol conversion units and channel management units are arranged to control the sequence of the received multiple access requests, and the accuracy of read data and written data is guaranteed when the memory is accessed in multiple ways.
Referring to fig. 7, an embodiment of the present application provides a block diagram of an electronic device, where the electronic device 400 includes a graphics processor 410 and a central processing unit 420.
The electronic device 400 may be a terminal device such as a tablet computer capable of running an application. The central processor 420 mainly processes an operating system, a user interface, an application program and the like; the graphics processor 410 is responsible for rendering and drawing of display content.
The graphics processor 410 includes memory in the foregoing embodiments that may be used to store instructions, programs, code sets, or instruction sets. Instructions for implementing at least one function (such as a touch function, a sound playing function, an image playing function, etc.), instructions for implementing various method embodiments described below, and so forth. The data storage area may also store data created by the electronic device 400 during use (e.g., phone books, audio-video data, chat log data), and the like.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While the preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all alterations and modifications as fall within the scope of the application.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.
Claims (10)
1. A memory, wherein the memory comprises a plurality of protocol conversion units, a channel management unit and a plurality of RAM banks;
the protocol conversion units are used for receiving access requests sent by a plurality of access request sources, performing protocol conversion on the access requests and sending the access requests to the channel management unit;
the channel management unit is used for allocating an arbitration management interface to each access request according to a preset sequence and accessing the RAM memory bank after arbitration is passed, the RAM memory bank is in one-to-one connection with the arbitration management interface, and the preset sequence is the sequence of receiving the access requests.
2. The memory according to claim 1, wherein the plurality of protocol conversion units are configured to send the plurality of protocol-converted access requests to the channel management unit according to the preset order.
3. The memory according to claim 2, wherein the protocol conversion unit includes a write data management subunit, a read data management subunit, and a read-write order management unit;
the write data management subunit is configured to receive corresponding write data when the access request is a write data request, convert the write data request into a write data transmission request carrying the write data, and send the write data transmission request to the channel management unit;
the read data management subunit is configured to, when the access request is a read data request, convert the read data request into a read data transmission request, and send the read data transmission request to the channel management unit; sending the read data returned by the channel management unit to a corresponding access request source;
and the read-write sequence management subunit is configured to control the read-data management subunit and the write-data management subunit, and send the write-data transmission request and the read-data transmission request according to the preset sequence.
4. The memory according to claim 3, wherein the read-write order management subunit is further configured to control the read-data management subunit to correspondingly send the read data returned by the channel management unit to the access request source according to a first order when an access conflict occurs, where the first order is an order in which the read-data management subunit receives the read-data requests.
5. The memory of claim 3, wherein the channel management unit comprises a plurality of address division subunits, a multi-master to multi-slave arbitration management subunit and a read-write consistency management subunit;
the multiple address division subunits are used for distributing multiple masters to multiple slaves arbitration management subunits according to access addresses carried in the write data transmission request or the read data transmission request;
the read-write consistency management subunit is used for sending the write data transmission request or the read data transmission request to the corresponding multi-master to multi-slave arbitration management subunit according to the preset sequence;
and the multi-master-to-multi-slave arbitration management subunit is used for sending the write data transmission request or the read data transmission request to the corresponding RAM memory bank through the arbitration management interface according to a first-in-first-out sequence.
6. The memory of claim 5, wherein the multi-master-to-multi-slave arbitration management subunit has a plurality of arbitration management interfaces, each arbitration management interface accessing the RAM banks in a first-in-first-out order.
7. The memory of claim 6, wherein the number of the protocol conversion units is the same for the address partitioning subunit, the arbitration management interface, and the protocol conversion units.
8. The memory of claim 7, wherein the memory is a Random Access Memory (RAM).
9. A Graphics Processor (GPU), comprising: a plurality of arithmetic units and a memory according to any one of claims 1-8.
10. An electronic device, comprising: a graphics processor in accordance with claim 9.
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| CN116107923A (en) * | 2022-12-27 | 2023-05-12 | 深存科技(无锡)有限公司 | BRAM-based many-to-many high-speed memory access architecture and memory access system |
| CN116661703A (en) * | 2023-07-03 | 2023-08-29 | 摩尔线程智能科技(北京)有限责任公司 | Memory access circuit, memory access method, integrated circuit, and electronic device |
| CN116719479A (en) * | 2023-07-03 | 2023-09-08 | 摩尔线程智能科技(北京)有限责任公司 | Memory access circuit, memory access method, integrated circuit, and electronic device |
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| CN116107923A (en) * | 2022-12-27 | 2023-05-12 | 深存科技(无锡)有限公司 | BRAM-based many-to-many high-speed memory access architecture and memory access system |
| CN116107923B (en) * | 2022-12-27 | 2024-01-23 | 深存科技(无锡)有限公司 | BRAM-based many-to-many high-speed memory access architecture and memory access system |
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| CN116737083A (en) * | 2023-07-03 | 2023-09-12 | 摩尔线程智能科技(北京)有限责任公司 | Memory access circuit, memory access method, integrated circuit, and electronic device |
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| CN116719479B (en) * | 2023-07-03 | 2024-02-20 | 摩尔线程智能科技(北京)有限责任公司 | Memory access circuit, memory access method, integrated circuit, and electronic device |
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