CN101777035A - Implementation method for AMBA AHB bus and device thereof - Google Patents
Implementation method for AMBA AHB bus and device thereof Download PDFInfo
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Abstract
The invention relates t6o an implementation method for an AMBA AHB bus and a device thereof, in the implementation method for the AMBA AHB bus, an AHB bus bridge for implementing the memory accessing of timing closure of the AHB bus is arranged between an AHB bus gating logic control unit and a primary device; the AHB bus gating logic control unit comprises an address and control multiplexer and a data-writing multiplexer, and an arbiter is respectively connected with the address and control multiplexer and the data-writing multiplexer. The method and the device can control logic complexity and maintain low-delay AHM transmission and smaller design area.
Description
Technical field
The present invention relates to the embedded system field, relate in particular to a kind of AMBA ahb bus implementation method and device.
Background technology
The development of the progress of semiconductor technology and integrated circuit (IC) design technology makes that the functional part of integrated total system becomes possibility on one chip, the main flow of the current integrated circuit of SoC design having become at present.The requirement of Time To Market (Time-to-Market) is more and more harsher, and for shortening design and proving period, the method for designing multiplexing based on IP (Intellectual Property) is widely adopted in the SoC design.On-chip bus (On Chip Bus) has solved the mutual communication issue between each IP functional module as the interconnection structure of SoC integrated system, comprises aspects such as data layout, sequential, agreement.The SoC on-chip bus technology of main flow is used and is disclosed general bus structure, the CoreConnect bus of the AMBA that mainly contains ARM company of comparative maturity (Advanced Microcontroller Bus Architecture) bus, IBM Corporation etc. in the world.
The immense success that ARM company obtains in the embedded microprocessor field, feasible bus structure based on AMBA become the bus architecture that the most extensively adopt in the embedded SoC field, have become the de facto standard of industry.The IP module that is integrated on the embedded system chip has the AMBA bus interface, and abundant IP storehouse is based on the huge advantage of the bus-structured embedded SoC of AMBA.The AMBA bus has been stipulated three kinds of bus standard: AHB (Advanced High-performance Bus), ASB (Advanced System Bus) and APB (Advanced Peripheral Bus).Continuous expansion along with the System on Chip/SoC scale, need be on one chip integrated more and more functional parts, how under the situation that system sequence becomes increasingly complex, reduce the delay of crucial timing path, the timing closure that reaches under the chip high-frequency becomes the significant challenge that the current main-stream System on Chip/SoC designs as far as possible.
Summary of the invention
In order to solve above-mentioned technical matters, kind AMBA ahb bus implementation method and device are provided, its purpose is, shortening is by the timing path of AHB, conveniently reach the timing closure under the bus high-frequency, put steering logic complexity as far as possible before this, keep low AHB transmission and the less design area that postpones.
The invention provides a kind of AMBA ahb bus implementation method, the ahb bus bridge is set between ahb bus gate logic control module and main equipment, be used to realize the timing closure of memory access ahb bus; Ahb bus gate logic control module comprises address and control multiplexer and write data multiplexer, and moderator is connected respectively with control multiplexer and write data multiplexer with the address.
For writing transaction, the ahb bus bridge is deposited address and the control signal that main equipment provides, write data and address and control signal; The ahb bus bridge is with the address and the control signal of depositing, and perhaps write data and address and control signal send to ahb bus for the slave unit collection;
For reading transaction, the ahb bus bridge is deposited address and the control signal that main equipment provides; The ahb bus bridge sends to ahb bus for the slave unit collection with the address and the control signal of depositing, and the read data that slave unit returns is sent to main equipment.
Send once single writing at main equipment and carry out following steps when concluding the business:
Step 11, ahb bus bridge are deposited address and control signal after finding that main equipment initiates once to write transaction;
Step 13, address after the ahb bus bridge will be deposited and control signal send on the ahb bus for the slave unit collection;
Step 14, the write data after the ahb bus bridge will be deposited send to and supply the slave unit collection on the bus, thereby realize once writing transaction.
Send once the single following steps of carrying out when reading to conclude the business at main equipment:
Step 21, ahb bus bridge are deposited address and control signal after finding that main equipment initiates once to read transaction;
Step 22, ahb bus bridge are carried out bus application and authorized;
Step 23, address after the ahb bus bridge will be deposited and control signal send on the ahb bus for the slave unit collection;
Step 24, after slave unit returned read data, the ahb bus bridge was deposited this read data;
Step 25, the read data after the ahb bus bridge will be deposited sends to main equipment, thereby realizes once reading transaction.
Sending a secondary burst at main equipment writes when transaction and carries out following steps:
Step 31, ahb bus bridge discovery main equipment initiates to deposit the 1st address and control signal after a secondary burst is write transaction;
Step 33, the write data of the 1st the address correspondence that the ahb bus bridge will be deposited and the 2nd address and control signal are sent to ahb bus for the slave unit collection, and the notice main equipment keeps the write data of the 2nd address correspondence and the 3rd address and control signal;
Step 34, for the write data of n-1 address correspondence and n address and control signal, the write data of n-2 the address correspondence that the ahb bus bridge will be deposited and n-1 address and control signal are sent to ahb bus for the slave unit collection, and the notice main equipment is with the write data of n-1 address correspondence and n address and control signal maintenance; N＞4, n is a natural number, n address is not last address;
Step 35, ahb bus bridge notice main equipment keeps the write data of last address correspondence and writes closing the transaction information and deposit the write data of last address correspondence and write closing the transaction information, with the write data of last address correspondence with write closing the transaction information and be sent to ahb bus, write closing the transaction for the slave unit collection.
Send at main equipment and to carry out following steps when the burst of fixed length reads to conclude the business:
Step 41, ahb bus bridge are found to deposit the 1st address and control signal after a fixed length burst of main equipment initiation reads to conclude the business;
Step 42, the ahb bus bridge carry out the bus application and authorized after, ahb bus bridge notice main equipment keeps the 2nd address and control signal and deposits the 2nd address and control signal, and the 1st address and the control signal of depositing is sent to ahb bus for the slave unit collection; Start timer, the value of preset timer is 3;
Step 43, ahb bus bridge are deposited the read data of the 1st the address correspondence that slave unit returns and the read data of the 1st address correspondence are sent to main equipment; The 2nd address and the control signal of depositing are sent to ahb bus for the slave unit collection, and the notice main equipment keeps the 3rd address and control signal, deposit the 3rd address and control signal;
Step 44, ahb bus bridge are deposited the read data of the 2nd the address correspondence that slave unit returns and the read data of the 2nd address correspondence are sent to main equipment; The 3rd address and the control signal of depositing are sent to ahb bus for the slave unit collection;
Step 45, the value of timer is 1 o'clock, ahb bus bridge notice main equipment is with the 4th address and read closing the transaction information and keep and deposit the 4th address and read closing the transaction information, with the 4th address with read closing the transaction information and be sent to ahb bus for the slave unit collection;
After step 46, ahb bus bridge receive the read data of the 4th the address correspondence that slave unit sends, the read data of the 4th address correspondence is sent to main equipment, reads closing the transaction.
Send at main equipment and to carry out following steps when the burst of random length reads to conclude the business:
Step 51, ahb bus bridge are found to deposit the 1st address and control signal after a fixed length burst of main equipment initiation reads to conclude the business;
Step 52, the ahb bus bridge carry out the bus application and authorized after, ahb bus bridge notice main equipment keeps the 2nd address and control signal and deposits the 2nd address and control signal, and the 1st address and the control signal of depositing is sent to ahb bus for the slave unit collection;
Step 53, ahb bus bridge are deposited the read data of the 1st the address correspondence that slave unit returns and the read data of the 1st address correspondence are sent to main equipment; The 2nd address and the control signal of depositing are sent to ahb bus for the slave unit collection, and the notice main equipment keeps the 3rd address and control signal, deposit the 3rd address and control signal;
Step 54, for n address and control signal, n-1 address that the ahb bus bridge will be deposited and control signal are sent to ahb bus for the slave unit collection, the notice main equipment keeps n address and control signal and deposits this n address and control signal, and the read data of depositing n-1 the address correspondence that slave unit returns also is sent to main equipment with this read data; N＞3, n is a natural number, n address is not last address;
Step 55, ahb bus bridge notice main equipment keep last address and read closing the transaction information and deposit last address and read closing the transaction information, with last address with read closing the transaction information and be sent to ahb bus for the slave unit collection; Behind the read data corresponding to last address that receives the slave unit transmission, the read data that the ahb bus bridge will be somebody's turn to do corresponding to last address is sent to main equipment, reads closing the transaction.
Initiate a random length burst transfer when main equipment and begin, if the data umber of beats of transmission less than 16, then moderator keeps the mandate to this main equipment; When the data umber of beats of transmission reached 16 bats, moderator carried out the ahb bus arbitration again.
Ahb bus gate logic control module also comprises the read data multiplexer when above when the quantity of slave unit is one, and the read data multiplexer is connected with demoder, ahb bus bridge and slave unit respectively.
The invention provides a kind of AMBA ahb bus implement device, comprise the ahb bus bridge, this ahb bus bridge is arranged between ahb bus gate logic control module and the main equipment, is used to realize the timing closure of memory access ahb bus; Ahb bus gate logic control module comprises address and control multiplexer and write data multiplexer, and moderator is connected respectively with control multiplexer and write data multiplexer with the address.
The ahb bus bridge is used for depositing address and the control signal that main equipment provides, write data and address and control signal when writing transaction; With the address and the control signal of depositing, perhaps write data and address and control signal send to ahb bus for the slave unit collection;
The ahb bus bridge is used for depositing address and the control signal that main equipment provides when reading to conclude the business; The address and the control signal of depositing are sent to ahb bus for the slave unit collection, and the read data that slave unit returns is sent to main equipment.
The ahb bus bridge is used for depositing address and control signal send once single when transaction write at main equipment; Carry out the bus application and authorized after, ahb bus bridge notice main equipment keeps write data, the ahb bus bridge is deposited write data; Address after depositing and control signal are sent on the ahb bus for the slave unit collection; Write data after depositing is sent to confession slave unit collection on the bus, thereby realize once writing transaction.
The ahb bus bridge is used for sending once single address and the control signal of depositing when reading to conclude the business at main equipment; Carry out bus application and authorized; Address after depositing and control signal are sent on the ahb bus for the slave unit collection; After slave unit returned read data, the ahb bus bridge was deposited this read data; Read data after depositing is sent to main equipment, thereby realize once reading transaction.
The ahb bus bridge is used for sending a secondary burst at main equipment and writes transaction and the time deposit the 1st address and control signal; Carry out the bus application and authorized after, ahb bus bridge notice main equipment keeps the write data of the 1st address correspondence and the 2nd address and control signal and deposits this write data and the 2nd address and control signal, and the 1st address and the control signal of depositing is sent to ahb bus for the slave unit collection; The write data of the 1st the address correspondence of depositing and the 2nd address and control signal are sent to ahb bus for the slave unit collection, and the notice main equipment keeps the write data of the 2nd address correspondence and the 3rd address and control signal; For the write data of n-1 address correspondence and n address and control signal, the write data of n-2 the address correspondence of depositing and n-1 address and control signal are sent to ahb bus for the slave unit collection, and the notice main equipment is with the write data of n-1 address correspondence and n address and control signal maintenance; N＞4, n is a natural number, n address is not last address; The notice main equipment keeps the write data of last address correspondence and writes closing the transaction information and deposit the write data of last address correspondence and write closing the transaction information, with the write data of last address correspondence with write closing the transaction information and be sent to ahb bus, write closing the transaction for the slave unit collection.
The ahb bus bridge is used for sending a fixed length burst at main equipment and deposits the 1st address and control signal when reading to conclude the business; Carry out the bus application and authorized after, the notice main equipment keeps the 2nd address and control signal and deposits the 2nd address and control signal, and the 1st address and the control signal of depositing is sent to ahb bus for the slave unit collection; Start timer, the value of preset timer is 3; Deposit the read data of the 1st the address correspondence that slave unit returns and the read data of the 1st address correspondence is sent to main equipment; The 2nd address and the control signal of depositing are sent to ahb bus for the slave unit collection, and the notice main equipment keeps the 3rd address and control signal, deposit the 3rd address and control signal; Deposit the read data of the 2nd the address correspondence that slave unit returns and the read data of the 2nd address correspondence is sent to main equipment; The 3rd address and the control signal of depositing are sent to ahb bus for the slave unit collection; The value of timer is 1 o'clock, and ahb bus bridge notice main equipment is with the 4th address and read closing the transaction information and keep and deposit the 4th address and read closing the transaction information, with the 4th address with read closing the transaction information and be sent to ahb bus for the slave unit collection; After receiving the read data of the 4th the address correspondence that slave unit sends, the read data of the 4th address correspondence is sent to main equipment, reads closing the transaction.
The ahb bus bridge is used for sending a random length burst at main equipment and deposits the 1st address and control signal when reading to conclude the business; Carry out the bus application and authorized after, the notice main equipment keeps the 2nd address and control signal and deposits the 2nd address and control signal, and the 1st address and the control signal of depositing is sent to ahb bus for the slave unit collection; Deposit the read data of the 1st the address correspondence that slave unit returns and the read data of the 1st address correspondence is sent to main equipment; The 2nd address and the control signal of depositing are sent to ahb bus for the slave unit collection, and the notice main equipment keeps the 3rd address and control signal, deposit the 3rd address and control signal; For n address and control signal, n-1 the address and the control signal of depositing are sent to ahb bus for the slave unit collection, the notice main equipment keeps n address and control signal and deposits this n address and control signal, and the read data of depositing n-1 the address correspondence that slave unit returns also is sent to main equipment with this read data; N＞3, n is a natural number, n address is not last address; The notice main equipment keeps last address and reads closing the transaction information and deposit last address and read closing the transaction information, with last address with read closing the transaction information and be sent to ahb bus for the slave unit collection; Behind the read data corresponding to last address that receives the slave unit transmission, the read data that the ahb bus bridge will be somebody's turn to do corresponding to last address is sent to main equipment, reads closing the transaction.
Initiate a random length burst transfer when main equipment and begin, if the data umber of beats of transmission less than 16, then moderator keeps the mandate to this main equipment; When the data umber of beats of transmission reached 16 bats, moderator carried out the ahb bus arbitration again.
Ahb bus gate logic control module also comprises the read data multiplexer when above when the quantity of slave unit is one, and the read data multiplexer is connected with demoder, ahb bus bridge and slave unit respectively.
The present invention can the steering logic complexity, keeps low AHB transmission and the less design area that postpones.
The present invention is according to the bus trade signal sequence of AMBA ahb bus agreement regulation, realized a kind of with all addresses on the ahb bus, the mechanism that control and data-signal are deposited, thereby overlength timing path on the potential ahb bus is blocked, conveniently reach timing closure, make AHB under higher frequency, to work.
Also realized the mechanism that a kind of burst transfer transaction regenerates, make and under the prerequisite that bus signals is deposited, keep the low AHB of delay transmission, calculate automatically the address of the burst transfer transaction of the AHB main equipment being sent according to AMBA ahb bus agreement, and carry out the inspection of 1K address boundary.
Also realized certain arbitration mechanism, guaranteed that the continuous 16 bat burst transfer of the transaction of same AHB main equipment on ahb bus are not interrupted.
Description of drawings
Fig. 1 is for being the SoC one-piece construction figure of high speed memory access bus with UniBus64;
Fig. 2 is general A MBA ahb bus modular structure figure;
Fig. 3 is the cut-away view of UniBus64;
Fig. 4 is the input/output signal of Reg_Brige modular design;
Fig. 5 is the single sequential explanation of writing transaction of Reg_Bridge resume module;
Fig. 6 is the single sequential explanation of reading to conclude the business of Reg_Brige resume module;
Fig. 7 writes the sequential explanation of transaction for the burst of Reg_Bridge resume module;
The sequential explanation that Fig. 8 reads to conclude the business for the burst of Reg_Bridge resume module fixed length;
The sequential explanation that Fig. 9 reads to conclude the business for the burst of Reg_Bridge resume module random length.
Embodiment
Below in conjunction with accompanying drawing, the present invention is described in further detail.
The System on Chip/SoC that the present invention relates to is exactly a main flow System on Chip/SoC Application Design towards multifunctional application, adopted AHB+APB bus architecture as a whole, its high speed memory access bus AHB (UniBus64) is responsible for carrying out processor (UniCore-II) and figure/image processing module (UniGFX) high speed accessing operation, high speed system bus AHB (32 AHB) is responsible for processor configuration peripherals and high-performance peripherals accessing operation, speed peripheral APB provides the interface of low bandwidth, connects low performance peripherals.Connect by the AHB2APB bridge between high speed system bus AHB and the speed peripheral APB and communicate by letter.
And in AMBA 2.0AHB agreement, propose in traditional ahb bus modular design, signal between AHB main equipment (Master) and the AHB slave unit (Slave) is mutual general only through a multi-selection device, on bus, do not deposit, therefore the maximum clock frequency of bus postpone 3 parts by main equipment internal bus signal delay, bus delay and slave unit internal bus and decision, this becomes and reaches the high speed memory access bus (UniBus64) that the present invention relates to and reach that memory access is low to be postponed, and timing closure is to the main bottleneck of high clock frequency.Patent in the past is United States Patent (USP) 7330911 for example, realized a kind of bus module design towards a plurality of AHB main equipment accessed peripheral, the inner form buffer memory bus signals that adopts linear buffer memory (Line Buffer) can be realized blocking of bus signals timing path between the master-slave equipment, be divided into timing path from notes equipment to linear buffer memory and linearity is cached to two parts of slave unit, but owing to AHB need be transmitted the accessing operation that convert to linear buffer memory, make the delay complicated and the visit peripheral hardware of this design inner control logic increase, add buffer memory itself and can make the area of design itself expand, realize cost thereby increase design.
The present invention has realized a kind of AMBA ahb bus implementation method and system of optimization, adopted simply deposited mechanism optimization sequential with bridge for the ahb bus signal in inside, is that truncation points is divided into two parts to the overlength timing path of memory controller inside with the internal bridged device with original processor or figure/image processing module directly by bus, under the less prerequisite of the extra steering logic area that increases, solved the difficult problem that high speed memory access bus timing converges to high clock frequency, and realized having guaranteed low delay accessing operation at the transaction address generting machanism and the arbitration mechanism of burst transfer in inside.
The present invention proposes a kind of high speed AMBA ahb bus implementation method and system towards timing closure.
Bus trade signal sequence according to AMBA ahb bus agreement regulation, realized a kind of with all addresses on the ahb bus, the mechanism that control and data-signal are deposited, thereby overlength timing path on the potential ahb bus is blocked, conveniently reach timing closure, make AHB under higher frequency, to work.
Also realized the mechanism that a kind of burst transfer transaction regenerates, make and under the prerequisite that bus signals is deposited, keep the low AHB of delay transmission, calculate automatically the address of the burst transfer transaction of the AHB main equipment being sent according to AMBA ahb bus agreement, and carry out the inspection of 1K address boundary.
Also realized certain arbitration mechanism, guaranteed that the continuous 16 bat burst transfer of the transaction of same AHB main equipment on ahb bus are not interrupted.
The system UniBus64 that the present invention realizes mainly comprises bus signals controlled to deposit and handles and bridge module (hereinafter to be referred as Reg_Bridge) and two parts of arbitration modules (Arbiter) that the transaction transport address regenerates.
Fig. 1 is for being the SoC one-piece construction figure of high speed memory access bus with UniBus64, and this is one the processor UniCore-II of independent development is applied to System on Chip/SoC based on AMBA ahb bus framework as bus control unit.In an embodiment of the present invention, UniBus64 is responsible for carrying out processor UniCore-II and graph and image processing parts UniGFX accessing operation, and its frequency of operation is huge to the memory access performance impact of total system chip.
Under the general AMBA ahb bus modular design that adopts AMBA 2.0AHB agreement regulation shown in Figure 2, through the sequential assessment, bus signals is not deposited under the prerequisite of processing in bus module inside, there are many overlength timing paths to memory controller inside from UniCore-II, make high speed memory access bus can't reach the timing closure under the high-frequency 600MHz.Therefore adopted the UniBus64 modular design of structure as shown in Figure 3 at embodiments of the invention, specifically having added the Reg_Bridge module deposits the input signal from master-slave equipment on the ahb bus, original overlength timing path is blocked, and the transaction timing variations on the bus of bringing is thus handled by the inner address robot brain system that realizes of Reg_Bridge.Continue to carry out the characteristic of random length burst transfer memory access in addition according to the needs of UniGFX, on arbitration mechanism, add 16 and clap the continuous burst transfer nonbreaking rule of concluding the business, guaranteed that UniBus64 can provide the low memory access support that postpones.Among Fig. 3, if there is plural slave unit, also need to be provided with read data multiplexer and demoder, slave unit is imported the read data multiplexer with reading data signal, then by read data multiplexer input Reg_Bridge module, need that simultaneously demoder is set reading data signal is decoded, read data multiplexer and demoder can be used existing techniques in realizing, as read data multiplexer and the demoder among Fig. 2.
Fig. 4 is the input/output signal signal of UniBus64 modular design, below specifically introduce the idiographic flow that Reg_Bridge handles the various transaction of stipulating in the AHB agreement based on these signal instruction, wherein adopted Counter Design to realize that needs carry out the pregenerated characteristic in address in burst transfer according to AHB agreement regulation.In the following specific embodiment, address information and control information occur simultaneously.
Send once the single transaction of writing for main equipment, as shown in Figure 5, when Reg_Bridge sees (hwrite_m is a logical one) after main equipment initiates once to write transmission, carry out the bus application in that the situation that does not have bus grant is next, simultaneously hready_out is changed to logical one, makes main equipment write data (hwdata_m) to be sent in following one-period.Reg_Bridge is changed to 1 with hbusreq and carries out the bus application, and authorized back (hgrant becomes logical one) is changed to logical zero with hready_out, allows main equipment that write data is kept.Next cycle, address after Reg_Bridge will deposit and control signal (haddr_out) send on the bus, for the slave unit collection, monitor hready_s simultaneously.If hready_s is a logical one, illustrate that slave unit correctly gathers address and control signal.Next cycle, the data-signal (hwdata_out) after Reg_Bridge will deposit sends on the bus, for the slave unit collection, monitors hready_s simultaneously.If hready_s is a logical one, illustrate that slave unit correctly gathers write data.So far, once write transaction and just successfully arrive slave unit through Reg_Bridge from main equipment.
Send once the single transaction of reading for main equipment, as shown in Figure 6, when Reg_Bridge sees (hwrite_m is a logical zero) after main equipment initiates once to read transaction, do not having to prepare to carry out the bus application under the situation of bus grant, simultaneously hready_out is changed to logical one, informs that main equipment Reg_Bridge has correctly deposited address and control signal.Reg_Bridge is changed to 1 with hbusreq and carries out the bus application then, and authorized back (hgrant becomes logical one) is changed to logical zero with hready_out.Address after next cycle Reg_Bridge will deposit and control signal (haddr_out) send on the bus, allow the slave unit collection, monitor hready_s simultaneously.If hready_s is a logical one, illustrate that slave unit correctly gathers address and control signal.Reg_Bridge then monitors hready_s, if hready_s is a logical one, illustrates that then slave unit has correctly returned read data (hrdata_s), deposits this read data.Next cycle, the read data (hrdata_out) after Reg_Bridge will deposit sends to main equipment, and to put hready_out be logical one, allows main equipment gather this data.Like this, once read transaction and just successfully arrive slave unit through Reg_Bridge, and return to main equipment through Reg_Bridge from slave unit from main equipment.
Send a secondary burst for main equipment and write transaction, as shown in Figure 7, when Reg_Bridge sees (hwrite_m is a logical one) after main equipment initiates once to write transaction, carry out the bus application in the next preparation of the situation that does not have bus grant hbusreq is changed to logical one, simultaneously hready_out is changed to logical one, makes main equipment write data (hwdata_m) and second address (A+4) and control signal to be sent in following one-period.To keep hbusreq be logical one to Reg_Bridge then, and authorized back (hgrant becomes logical one) is changed to logical zero with hready_out, allows main equipment that write data and second address and control signal are kept.Next cycle, address after Reg_Bridge will deposit and control signal (haddr_out) send on the bus, for the slave unit collection, monitor address and control signal that hready_s and main equipment send simultaneously.If hready_s is a logical one, illustrate that slave unit correctly gathers address and control signal; Simultaneously because main equipment continues to send new address (A+4) and control signal, illustrate that main equipment need be proceeded to happen suddenly to write.Next cycle, the data-signal after Reg_Bridge will deposit and second address signal (haddr_out) and control signal send on the bus, for the slave unit collection, monitor hready_s simultaneously.If hready_s is a logical one, illustrate that slave unit correctly gathers write data and second address signal and control signal, because main equipment continues to send new address and control signal, showing further to happen suddenly writes transaction.No longer send new address up to main equipment control signal is changed to IDLE, illustrate that main equipment stops to send.At last, Reg_Bridge will remain write data and write.It should be noted that in addition transaction is write in burst for random length, the processing procedure of Reg_Bridge and fixed length are write transaction does not have any difference, repeats no more herein.
Send a fixed length burst for main equipment and read transaction, as shown in Figure 8, when Reg_Bridge sees (hwrite_m is a logical zero) after main equipment initiates once to read transaction, hbusreq is not changed to logical one having under the situation of bus grant to prepare the carrying out bus application, simultaneously hready_out is changed to logical one, makes main equipment second address (A+4) and control signal to be sent in following one-period.Reg_Bridge keep hbusreq be logical one up to authorized (hgrant=1), simultaneously hready_out is changed to logical zero, allow main equipment that second address and control signal are kept.Address after next cycle Reg_Bridge will deposit and control signal (haddr_out) send on the bus, and for the slave unit collection, and still to put hready_out be 0, makes main equipment still keep second address and control signal; In addition, utilize the hburst signal to come counter counter is carried out assignment,, therefore counter is composed initial value 3 owing to be the burst transfer of 4 bat fixed length.Simultaneously, Reg_Bridge monitors hready_s, if hready_s is a logical one, illustrates that slave unit correctly gathers address and control signal.Next cycle, Reg_Bridge still is changed to logical zero with hready_out, makes main equipment keep second address and control signal, and receives the data that slave unit returns according to the value of hready_s, and it is deposited; Simultaneously, utilize second address of register value generation and the control signal (haddr_out) of haddr_m signal to send on the bus, because be the fixed length burst transfer this moment, the value that main equipment continues to send new address and control signal and counter is not 1, and illustrating still has new transmission to carry out.Next cycle, Reg_Bridge is changed to logical one with hready_out, makes main equipment can access data.Become 1 up to counter, illustrate last address and control signal are sent on the bus.Next cycle, Reg_Bridge have been accepted last read data.At last, Reg_Bridge sends to main equipment with last data, thereby makes whole closing the transaction.
Send the burst of random length for main equipment and read transaction, as shown in Figure 9, owing to do not know the length transmitted, so the value of counter can't pre-determine, therefore burst is read transaction and is needed special processing to random length.Main equipment is initiated after the transaction, if there is not bus grant, the operation of Reg_Bridge application bus is above-mentioned reads consistent with the processing fixed length.Address after Reg_Bridge will deposit and control signal (haddr_out) send on the bus, and for the slave unit collection, and still to put hready_out be 0, makes main equipment still keep second address and control signal; In addition, utilizing the register value of hburst signal to come counter counter is carried out assignment, owing to be the burst transfer of random length, therefore counter is composed initial value 1, and be maintained 1 and send last up to main equipment and clap the address, is clearly 0.Simultaneously, Reg_Bridge monitors hready_s, if hready_s is a logical one, illustrates that slave unit correctly gathers address and control signal.Next cycle, Reg_Bridge still is changed to logical zero with hready_out, makes main equipment keep second address and control signal, and receives the data that slave unit returns according to the value of hready_s, and it is deposited; Simultaneously, utilize address signal (haddr_m) that main equipment sends and control signal to deposit to produce second address and control signal sends on the bus, because sent new address and control signal for random length burst transfer and main equipment this moment, illustrating still has subsequent transmission to carry out.Next cycle Reg_Bridge is changed to logical one with hready_out, makes main equipment can obtain data and sends next transaction.And so forth, no longer send new address, address and control signal are changed to the state of IDLE up to main equipment.As seen read transaction for random length, can go out two transaction to the slave unit pilosity generally speaking.These two trade fairs are seen by slave unit, but are transparent for main equipment.
With respect to the design of the traditional bus module of not depositing, by top description as can be known UniBus64 write transaction (comprising single and burst transfer) for each, under the ready at any time ideal conditions of slave unit, can cause the delay of bus cycles.And read transaction for each, then can cause the delay of two bus cycles.In the reality evaluation and test, because controlling it, storage generally finishes the stand-by period that all needs tens to tens bus cycles for the first count of each reading and writing transaction, therefore, for writing transaction, can not cause extra loss basically.And for reading transmission, the general delay that also only can increase one-period at the end of each transaction.And adopted inner mechanism of depositing, bus design can reach the timing closure of high frequency.Therefore, by having adopted the UniBus64 design of having optimized, be that the transmission delay of unit does not have under the situation of significant change with bus cycles, bus frequency has obtained significantly increasing, thereby makes the bus bandwidth to have obtained improvement to a great extent.
Need to prove, Reg_Bridge has not only realized reading in the burst transfer burst transfer address generting machanism based on counter in above-mentioned fixed length and random length, similar address generting machanism has also been realized in the address that the backrush (Wrapping) of stipulating for the AHB agreement happens suddenly in reading to conclude the business, and carries out the address check on 1kB border in whole mechanism.The situation on 1kB border is striden in the address that generates for the Reg_Bridge home address, and Reg_Bridge adopts the mode of inserting the IDLE state on bus to guarantee that the burst transfer address that Reg_Bridge sends can not stride the 1kB border.
A lot of AHB main equipments can send random length transaction (non-defined burst).And the random length transaction has multiple treatment mechanism for bus arbiter (arbiter), can guarantee promptly that main equipment " is not died of hunger " and how to handle, and can guarantee again can not bring the unnecessary delay loss because of the random length transmission.In the bus arbiter design of UniBus64, implemented a kind of burst transfer 16 that guarantees and clapped the Special arbitration mechanism that is not interrupted.Specific as follows, when beginning to initiate a random length burst transfer, a main equipment begins, arbiter can count the umber of beats that completes successfully, the transmission the data umber of beats less than 16 situation under, arbiter can keep the mandate (keeping its hgrant is logical one) for this main equipment.When reaching 16 bats, can arbitrate again according to the application situation and the priority of bus.At this moment, former main equipment may lose bus grant (its hgrant becomes logical zero).
Those skilled in the art can also carry out various modifications to above content under the condition that does not break away from the definite the spirit and scope of the present invention of claims.Therefore scope of the present invention is not limited in above explanation, but determine by the scope of claims.
Claims (18)
1. an AMBA ahb bus implementation method is characterized in that, the ahb bus bridge is set between ahb bus gate logic control module and main equipment, is used to realize the timing closure of memory access ahb bus; Ahb bus gate logic control module comprises address and control multiplexer and write data multiplexer, and moderator is connected respectively with control multiplexer and write data multiplexer with the address.
2. AMBA ahb bus implementation method as claimed in claim 1 is characterized in that,
For writing transaction, the ahb bus bridge is deposited address and the control signal that main equipment provides, write data and address and control signal; The ahb bus bridge is with the address and the control signal of depositing, and perhaps write data and address and control signal send to ahb bus for the slave unit collection;
For reading transaction, the ahb bus bridge is deposited address and the control signal that main equipment provides; The ahb bus bridge sends to ahb bus for the slave unit collection with the address and the control signal of depositing, and the read data that slave unit returns is sent to main equipment.
3. AMBA ahb bus implementation method as claimed in claim 2 is characterized in that, sends once single writing at main equipment and carries out following steps when concluding the business:
Step 11, ahb bus bridge are deposited address and control signal after finding that main equipment initiates once to write transaction;
Step 12, ahb bus bridge carry out the bus application and authorized after, ahb bus bridge notice main equipment keeps write data, the ahb bus bridge is deposited write data;
Step 13, address after the ahb bus bridge will be deposited and control signal send on the ahb bus for the slave unit collection;
Step 14, the write data after the ahb bus bridge will be deposited send to and supply the slave unit collection on the bus, thereby realize once writing transaction.
4. AMBA ahb bus implementation method as claimed in claim 2 is characterized in that, sends once the single following steps of carrying out when reading to conclude the business at main equipment:
Step 21, ahb bus bridge are deposited address and control signal after finding that main equipment initiates once to read transaction;
Step 22, ahb bus bridge are carried out bus application and authorized;
Step 23, address after the ahb bus bridge will be deposited and control signal send on the ahb bus for the slave unit collection;
Step 24, after slave unit returned read data, the ahb bus bridge was deposited this read data;
Step 25, the read data after the ahb bus bridge will be deposited sends to main equipment, thereby realizes once reading transaction.
5. AMBA ahb bus implementation method as claimed in claim 2 is characterized in that, sends at main equipment and carries out following steps when a secondary burst is write transaction:
Step 31, ahb bus bridge discovery main equipment initiates to deposit the 1st address and control signal after a secondary burst is write transaction;
Step 32, the ahb bus bridge carry out the bus application and authorized after, ahb bus bridge notice main equipment keeps the write data of the 1st address correspondence and the 2nd address and control signal and deposits this write data and the 2nd address and control signal, and the 1st address and the control signal of depositing is sent to ahb bus for the slave unit collection;
Step 33, the write data of the 1st the address correspondence that the ahb bus bridge will be deposited and the 2nd address and control signal are sent to ahb bus for the slave unit collection, and the notice main equipment keeps the write data of the 2nd address correspondence and the 3rd address and control signal;
Step 34, for the write data of n-1 address correspondence and n address and control signal, the write data of n-2 the address correspondence that the ahb bus bridge will be deposited and n-1 address and control signal are sent to ahb bus for the slave unit collection, and the notice main equipment is with the write data of n-1 address correspondence and n address and control signal maintenance; N＞4, n is a natural number, n address is not last address;
Step 35, ahb bus bridge notice main equipment keeps the write data of last address correspondence and writes closing the transaction information and deposit the write data of last address correspondence and write closing the transaction information, with the write data of last address correspondence with write closing the transaction information and be sent to ahb bus, write closing the transaction for the slave unit collection.
6. AMBA ahb bus implementation method as claimed in claim 2 is characterized in that, sends at main equipment and carries out following steps when a fixed length burst reads to conclude the business:
Step 41, ahb bus bridge are found to deposit the 1st address and control signal after a fixed length burst of main equipment initiation reads to conclude the business;
Step 42, the ahb bus bridge carry out the bus application and authorized after, ahb bus bridge notice main equipment keeps the 2nd address and control signal and deposits the 2nd address and control signal, and the 1st address and the control signal of depositing is sent to ahb bus for the slave unit collection; Start timer, the value of preset timer is 3;
Step 43, ahb bus bridge are deposited the read data of the 1st the address correspondence that slave unit returns and the read data of the 1st address correspondence are sent to main equipment; The 2nd address and the control signal of depositing are sent to ahb bus for the slave unit collection, and the notice main equipment keeps the 3rd address and control signal, deposit the 3rd address and control signal;
Step 44, ahb bus bridge are deposited the read data of the 2nd the address correspondence that slave unit returns and the read data of the 2nd address correspondence are sent to main equipment; The 3rd address and the control signal of depositing are sent to ahb bus for the slave unit collection;
Step 45, the value of timer is 1 o'clock, ahb bus bridge notice main equipment is with the 4th address and read closing the transaction information and keep and deposit the 4th address and read closing the transaction information, with the 4th address with read closing the transaction information and be sent to ahb bus for the slave unit collection;
After step 46, ahb bus bridge receive the read data of the 4th the address correspondence that slave unit sends, the read data of the 4th address correspondence is sent to main equipment, reads closing the transaction.
7. AMBA ahb bus implementation method as claimed in claim 2 is characterized in that, sends at main equipment and carries out following steps when a random length burst reads to conclude the business:
Step 51, ahb bus bridge are found to deposit the 1st address and control signal after a fixed length burst of main equipment initiation reads to conclude the business;
Step 52, the ahb bus bridge carry out the bus application and authorized after, ahb bus bridge notice main equipment keeps the 2nd address and control signal and deposits the 2nd address and control signal, and the 1st address and the control signal of depositing is sent to ahb bus for the slave unit collection;
Step 53, ahb bus bridge are deposited the read data of the 1st the address correspondence that slave unit returns and the read data of the 1st address correspondence are sent to main equipment; The 2nd address and the control signal of depositing are sent to ahb bus for the slave unit collection, and the notice main equipment keeps the 3rd address and control signal, deposit the 3rd address and control signal;
Step 54, for n address and control signal, n-1 address that the ahb bus bridge will be deposited and control signal are sent to ahb bus for the slave unit collection, the notice main equipment keeps n address and control signal and deposits this n address and control signal, and the read data of depositing n-1 the address correspondence that slave unit returns also is sent to main equipment with this read data; N＞3, n is a natural number, n address is not last address;
Step 55, ahb bus bridge notice main equipment keep last address and read closing the transaction information and deposit last address and read closing the transaction information, with last address with read closing the transaction information and be sent to ahb bus for the slave unit collection; Behind the read data corresponding to last address that receives the slave unit transmission, the read data that the ahb bus bridge will be somebody's turn to do corresponding to last address is sent to main equipment, reads closing the transaction.
8. AMBA ahb bus implementation method as claimed in claim 2 is characterized in that, initiate a random length burst transfer when main equipment and begin, if the data umber of beats of transmission less than 16, then moderator keeps the mandate to this main equipment; When the data umber of beats of transmission reached 16 bats, moderator carried out the ahb bus arbitration again.
9. AMBA ahb bus implementation method as claimed in claim 2, it is characterized in that, ahb bus gate logic control module also comprises the read data multiplexer when above when the quantity of slave unit is one, and the read data multiplexer is connected with demoder, ahb bus bridge and slave unit respectively.
10. an AMBA ahb bus implement device is characterized in that, comprises the ahb bus bridge, and this ahb bus bridge is arranged between ahb bus gate logic control module and the main equipment, is used to realize the timing closure of memory access ahb bus; Ahb bus gate logic control module comprises address and control multiplexer and write data multiplexer, and moderator is connected respectively with control multiplexer and write data multiplexer with the address.
11. AMBA ahb bus implement device as claimed in claim 10 is characterized in that,
The ahb bus bridge is used for depositing address and the control signal that main equipment provides, write data and address and control signal when writing transaction; With the address and the control signal of depositing, perhaps write data and address and control signal send to ahb bus for the slave unit collection;
The ahb bus bridge is used for depositing address and the control signal that main equipment provides when reading to conclude the business; The address and the control signal of depositing are sent to ahb bus for the slave unit collection, and the read data that slave unit returns is sent to main equipment.
12. AMBA ahb bus implement device as claimed in claim 11 is characterized in that,
The ahb bus bridge is used for depositing address and control signal send once single when transaction write at main equipment; Carry out the bus application and authorized after, ahb bus bridge notice main equipment keeps write data, the ahb bus bridge is deposited write data; Address after depositing and control signal are sent on the ahb bus for the slave unit collection; Write data after depositing is sent to confession slave unit collection on the bus, thereby realize once writing transaction.
13. AMBA ahb bus implement device as claimed in claim 12 is characterized in that, the ahb bus bridge is used for sending once single address and the control signal of depositing when reading to conclude the business at main equipment; Carry out bus application and authorized; Address after depositing and control signal are sent on the ahb bus for the slave unit collection; After slave unit returned read data, the ahb bus bridge was deposited this read data; Read data after depositing is sent to main equipment, thereby realize once reading transaction.
14. AMBA ahb bus implement device as claimed in claim 12 is characterized in that, the ahb bus bridge is used for sending a secondary burst at main equipment and writes transaction and the time deposit the 1st address and control signal; Carry out the bus application and authorized after, ahb bus bridge notice main equipment keeps the write data of the 1st address correspondence and the 2nd address and control signal and deposits this write data and the 2nd address and control signal, and the 1st address and the control signal of depositing is sent to ahb bus for the slave unit collection; The write data of the 1st the address correspondence of depositing and the 2nd address and control signal are sent to ahb bus for the slave unit collection, and the notice main equipment keeps the write data of the 2nd address correspondence and the 3rd address and control signal; For the write data of n-1 address correspondence and n address and control signal, the write data of n-2 the address correspondence of depositing and n-1 address and control signal are sent to ahb bus for the slave unit collection, and the notice main equipment is with the write data of n-1 address correspondence and n address and control signal maintenance; N＞4, n is a natural number, n address is not last address; The notice main equipment keeps the write data of last address correspondence and writes closing the transaction information and deposit the write data of last address correspondence and write closing the transaction information, with the write data of last address correspondence with write closing the transaction information and be sent to ahb bus, write closing the transaction for the slave unit collection.
15. AMBA ahb bus implement device as claimed in claim 12 is characterized in that, the ahb bus bridge is used for sending a fixed length burst at main equipment and deposits the 1st address and control signal when reading to conclude the business; Carry out the bus application and authorized after, the notice main equipment keeps the 2nd address and control signal and deposits the 2nd address and control signal, and the 1st address and the control signal of depositing is sent to ahb bus for the slave unit collection; Start timer, the value of preset timer is 3; Deposit the read data of the 1st the address correspondence that slave unit returns and the read data of the 1st address correspondence is sent to main equipment; The 2nd address and the control signal of depositing are sent to ahb bus for the slave unit collection, and the notice main equipment keeps the 3rd address and control signal, deposit the 3rd address and control signal; Deposit the read data of the 2nd the address correspondence that slave unit returns and the read data of the 2nd address correspondence is sent to main equipment; The 3rd address and the control signal of depositing are sent to ahb bus for the slave unit collection; The value of timer is 1 o'clock, and ahb bus bridge notice main equipment is with the 4th address and read closing the transaction information and keep and deposit the 4th address and read closing the transaction information, with the 4th address with read closing the transaction information and be sent to ahb bus for the slave unit collection; After receiving the read data of the 4th the address correspondence that slave unit sends, the read data of the 4th address correspondence is sent to main equipment, reads closing the transaction.
16. AMBA ahb bus implement device as claimed in claim 12 is characterized in that, the ahb bus bridge is used for sending a random length burst at main equipment and deposits the 1st address and control signal when reading to conclude the business; Carry out the bus application and authorized after, the notice main equipment keeps the 2nd address and control signal and deposits the 2nd address and control signal, and the 1st address and the control signal of depositing is sent to ahb bus for the slave unit collection; Deposit the read data of the 1st the address correspondence that slave unit returns and the read data of the 1st address correspondence is sent to main equipment; The 2nd address and the control signal of depositing are sent to ahb bus for the slave unit collection, and the notice main equipment keeps the 3rd address and control signal, deposit the 3rd address and control signal; For n address and control signal, n-1 the address and the control signal of depositing are sent to ahb bus for the slave unit collection, the notice main equipment keeps n address and control signal and deposits this n address and control signal, and the read data of depositing n-1 the address correspondence that slave unit returns also is sent to main equipment with this read data; N＞3, n is a natural number, n address is not last address; The notice main equipment keeps last address and reads closing the transaction information and deposit last address and read closing the transaction information, with last address with read closing the transaction information and be sent to ahb bus for the slave unit collection; Behind the read data corresponding to last address that receives the slave unit transmission, the read data that the ahb bus bridge will be somebody's turn to do corresponding to last address is sent to main equipment, reads closing the transaction.
17. AMBA ahb bus implement device as claimed in claim 12 is characterized in that, initiate a random length burst transfer when main equipment and begin, if the data umber of beats of transmission less than 16, then moderator keeps the mandate to this main equipment; When the data umber of beats of transmission reached 16 bats, moderator carried out the ahb bus arbitration again.
18. AMBA ahb bus implement device as claimed in claim 12, it is characterized in that, ahb bus gate logic control module also comprises the read data multiplexer when above when the quantity of slave unit is one, and the read data multiplexer is connected with demoder, ahb bus bridge and slave unit respectively.
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| CN201010034229A CN101777035A (en) | 2010-01-14 | 2010-01-14 | Implementation method for AMBA AHB bus and device thereof |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104216856A (en) * | 2014-09-23 | 2014-12-17 | 天津国芯科技有限公司 | Bus bridge between DCR (Device Control Register) bus and APB (Advanced Peripheral Bus) |
| CN107025188A (en) * | 2016-01-29 | 2017-08-08 | 后旺科技股份有限公司 | Method is held in the friendship of combined type hard disk |
| CN113918497A (en) * | 2021-12-10 | 2022-01-11 | 苏州浪潮智能科技有限公司 | System, method and server for optimizing AHB bus data transmission performance |
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2010
- 2010-01-14 CN CN201010034229A patent/CN101777035A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104216856A (en) * | 2014-09-23 | 2014-12-17 | 天津国芯科技有限公司 | Bus bridge between DCR (Device Control Register) bus and APB (Advanced Peripheral Bus) |
| CN104216856B (en) * | 2014-09-23 | 2017-05-03 | 天津国芯科技有限公司 | Bus bridge between DCR (Device Control Register) bus and APB (Advanced Peripheral Bus) |
| CN107025188A (en) * | 2016-01-29 | 2017-08-08 | 后旺科技股份有限公司 | Method is held in the friendship of combined type hard disk |
| CN113918497A (en) * | 2021-12-10 | 2022-01-11 | 苏州浪潮智能科技有限公司 | System, method and server for optimizing AHB bus data transmission performance |
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