FI20155262L - Ohjelmoitava logiikkalaite ja sen varmennusmenetelmä - Google Patents

Ohjelmoitava logiikkalaite ja sen varmennusmenetelmä Download PDF

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Publication number
FI20155262L
FI20155262L FI20155262A FI20155262A FI20155262L FI 20155262 L FI20155262 L FI 20155262L FI 20155262 A FI20155262 A FI 20155262A FI 20155262 A FI20155262 A FI 20155262A FI 20155262 L FI20155262 L FI 20155262L
Authority
FI
Finland
Prior art keywords
programmable logic
logic device
status information
unit
verification method
Prior art date
Application number
FI20155262A
Other languages
English (en)
Finnish (fi)
Swedish (sv)
Inventor
Shuji Hamada
Yukitaka Yoshida
Atsushi Kojima
Original Assignee
Toshiba Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Kk filed Critical Toshiba Kk
Publication of FI20155262L publication Critical patent/FI20155262L/fi

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3177—Testing of logic operation, e.g. by logic analysers
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318516—Test of programmable logic devices [PLDs]
    • G01R31/318519—Test of field programmable gate arrays [FPGA]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/17764—Structural details of configuration resources for reliability
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748—Structural details of configuration resources
    • H03K19/17768—Structural details of configuration resources for security

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Security & Cryptography (AREA)
  • Logic Circuits (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
FI20155262A 2012-09-14 2013-09-11 Ohjelmoitava logiikkalaite ja sen varmennusmenetelmä FI20155262L (fi)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2012203486A JP5818762B2 (ja) 2012-09-14 2012-09-14 プログラマブルロジックデバイス及びその検証方法
PCT/JP2013/074534 WO2014042190A1 (fr) 2012-09-14 2013-09-11 Dispositif à logique programmable et procédé de validation

Publications (1)

Publication Number Publication Date
FI20155262L true FI20155262L (fi) 2015-04-10

Family

ID=50278300

Family Applications (1)

Application Number Title Priority Date Filing Date
FI20155262A FI20155262L (fi) 2012-09-14 2013-09-11 Ohjelmoitava logiikkalaite ja sen varmennusmenetelmä

Country Status (4)

Country Link
US (1) US20150204944A1 (fr)
JP (1) JP5818762B2 (fr)
FI (1) FI20155262L (fr)
WO (1) WO2014042190A1 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6784259B2 (ja) * 2015-09-02 2020-11-11 日本電気株式会社 プログラマブル論理集積回路と半導体装置およびキャラクタライズ方法
FR3063855B1 (fr) * 2017-03-08 2019-04-12 Areva Np Circuit logique programmable de commande d'une installation electrique, en particulier une installation nucleaire, dispositif et procede de commande associes
CN111832241A (zh) * 2020-07-03 2020-10-27 京微齐力(北京)科技有限公司 一种fpga多区域动态参数时序驱动设计方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06160491A (ja) * 1992-11-24 1994-06-07 Kawasaki Steel Corp 順序回路
JPWO2007113940A1 (ja) * 2006-04-04 2009-08-13 パナソニック株式会社 半導体検査装置
US8024614B2 (en) * 2006-08-14 2011-09-20 Nec Corporation Debugger and debugging method for debugging a system-on-chip device including a microprocessor core
JP5259082B2 (ja) * 2006-12-21 2013-08-07 三菱電機株式会社 一致検証方法及び装置
US7814444B2 (en) * 2007-04-13 2010-10-12 Synopsys, Inc. Scan compression circuit and method of design therefor
US8819507B2 (en) * 2010-05-10 2014-08-26 Raytheon Company Field programmable gate arrays with built-in self test mechanisms
US8856602B2 (en) * 2011-12-20 2014-10-07 International Business Machines Corporation Multi-core processor with internal voting-based built in self test (BIST)
US8694951B1 (en) * 2012-10-02 2014-04-08 Lsi Corporation Core wrapping in the presence of an embedded wrapped core

Also Published As

Publication number Publication date
US20150204944A1 (en) 2015-07-23
JP2014060537A (ja) 2014-04-03
WO2014042190A1 (fr) 2014-03-20
JP5818762B2 (ja) 2015-11-18

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