FI20070880L - Menetelmä RFIC:n suorituskyvyn alenemisen kompensoimiseksi käyttämällä EM simulointia (2006.01)ALI - Google Patents

Menetelmä RFIC:n suorituskyvyn alenemisen kompensoimiseksi käyttämällä EM simulointia (2006.01)ALI Download PDF

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Publication number
FI20070880L
FI20070880L FI20070880A FI20070880A FI20070880L FI 20070880 L FI20070880 L FI 20070880L FI 20070880 A FI20070880 A FI 20070880A FI 20070880 A FI20070880 A FI 20070880A FI 20070880 L FI20070880 L FI 20070880L
Authority
FI
Finland
Prior art keywords
rfic
compensating
simulation
utilizing
procedure
Prior art date
Application number
FI20070880A
Other languages
English (en)
Swedish (sv)
Other versions
FI20070880A0 (fi
Inventor
Yu Sin Kim
Chang Seok Lee
Kwang Du Lee
Hak Sun Kim
Chang Soo Yang
Original Assignee
Samsung Electro Mech
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electro Mech filed Critical Samsung Electro Mech
Publication of FI20070880A0 publication Critical patent/FI20070880A0/fi
Publication of FI20070880L publication Critical patent/FI20070880L/fi

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/36—Circuit design at the analogue level
    • G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Software Systems (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
FI20070880A 2006-11-21 2007-11-19 Menetelmä RFIC:n suorituskyvyn alenemisen kompensoimiseksi käyttämällä EM simulointia (2006.01)ALI FI20070880L (fi)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020060114964A KR100844496B1 (ko) 2006-11-21 2006-11-21 Ｅｍ 시뮬레이션을 이용한 ｒｆｉｃ의 성능 열화 보상 방법

Publications (2)

Publication Number Publication Date
FI20070880A0 FI20070880A0 (fi) 2007-11-19
FI20070880L true FI20070880L (fi) 2008-05-22

Family

ID=38786665

Family Applications (1)

Application Number Title Priority Date Filing Date
FI20070880A FI20070880L (fi) 2006-11-21 2007-11-19 Menetelmä RFIC:n suorituskyvyn alenemisen kompensoimiseksi käyttämällä EM simulointia (2006.01)ALI

Country Status (4)

Country Link
US (1) US7954079B2 (fi)
KR (1) KR100844496B1 (fi)
CN (1) CN101187954B (fi)
FI (1) FI20070880L (fi)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7933845B1 (en) 2004-07-27 2011-04-26 Stamps.Com Inc. Image-customization of computer-based value-bearing items
US10839332B1 (en) 2006-06-26 2020-11-17 Stamps.Com Image-customized labels adapted for bearing computer-based, generic, value-bearing items, and systems and methods for providing image-customized labels
US8505978B1 (en) 2006-12-20 2013-08-13 Stamps.Com Inc. Systems and methods for creating and providing shape-customized, computer-based, value-bearing items
US8327305B1 (en) * 2009-07-31 2012-12-04 Altera Corporation Voltage drop aware circuit placement
CN103455691A (zh) * 2013-09-25 2013-12-18 浪潮电子信息产业股份有限公司 一种简化的cct前仿真方法
CN103973291B (zh) 2014-04-22 2017-02-01 华为技术有限公司 射频天线开关
CN105447222B (zh) * 2014-09-22 2018-09-25 台湾积体电路制造股份有限公司 用于集成电路的工艺变化分析的方法
KR20170133750A (ko) * 2016-05-26 2017-12-06 삼성전자주식회사 집적 회로의 설계를 위한 컴퓨터 구현 방법
CN106100761A (zh) * 2016-06-07 2016-11-09 上海传英信息技术有限公司 射频电路调试方法
US10909302B1 (en) * 2019-09-12 2021-02-02 Cadence Design Systems, Inc. Method, system, and computer program product for characterizing electronic designs with electronic design simplification techniques
US11101905B1 (en) 2020-07-08 2021-08-24 Keysight Technologies, Inc. Method for estimating radiative contamination at nodes of an RF circuit

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6286128B1 (en) * 1998-02-11 2001-09-04 Monterey Design Systems, Inc. Method for design optimization using logical and physical information
JP2000035982A (ja) 1998-07-21 2000-02-02 Mitsubishi Electric Corp Ｌｓｉ設計用検証装置
US6061283A (en) * 1998-10-23 2000-05-09 Advantest Corp. Semiconductor integrated circuit evaluation system
JP2001117960A (ja) 1999-10-20 2001-04-27 Matsushita Electric Ind Co Ltd 論理シミュレーション方法
JP2002197133A (ja) 2000-10-17 2002-07-12 Hitachi Ltd 半導体集積回路の設計方法、データ処理システム、データ処理方法、及びアナログ・ディジタル混載集積回路の設計方法
JP2003124321A (ja) 2001-10-18 2003-04-25 Seiko Epson Corp 半導体集積回路及びその設計方法
US7152215B2 (en) * 2002-06-07 2006-12-19 Praesagus, Inc. Dummy fill for integrated circuits
JP2004318316A (ja) 2003-04-14 2004-11-11 Toshiba Solutions Corp 半導体設計支援装置、方法及びプログラム
JP2005267019A (ja) 2004-03-17 2005-09-29 Matsushita Electric Ind Co Ltd 半導体集積回路の設計方法及び設計装置

Also Published As

Publication number Publication date
KR20080045826A (ko) 2008-05-26
CN101187954B (zh) 2012-08-08
US20080134112A1 (en) 2008-06-05
KR100844496B1 (ko) 2008-07-08
US7954079B2 (en) 2011-05-31
FI20070880A0 (fi) 2007-11-19
CN101187954A (zh) 2008-05-28

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