FI104392B - Demultiplekserin rekisteriosoitus - Google Patents

Demultiplekserin rekisteriosoitus Download PDF

Info

Publication number
FI104392B
FI104392B FI961039A FI961039A FI104392B FI 104392 B FI104392 B FI 104392B FI 961039 A FI961039 A FI 961039A FI 961039 A FI961039 A FI 961039A FI 104392 B FI104392 B FI 104392B
Authority
FI
Finland
Prior art keywords
address
microprocessor
memory device
multiplexer
memory
Prior art date
Application number
FI961039A
Other languages
English (en)
Finnish (fi)
Swedish (sv)
Other versions
FI961039A0 (fi
FI961039L (fi
Inventor
Reino Hiltunen
Original Assignee
Nokia Satellite Systems Ab
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nokia Satellite Systems Ab filed Critical Nokia Satellite Systems Ab
Priority to FI961039A priority Critical patent/FI104392B/fi
Publication of FI961039A0 publication Critical patent/FI961039A0/fi
Priority to EP97102622A priority patent/EP0794486A3/de
Publication of FI961039L publication Critical patent/FI961039L/fi
Application granted granted Critical
Publication of FI104392B publication Critical patent/FI104392B/fi

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a secondary processor, e.g. coprocessor
    • G06F9/3879—Concurrent instruction execution, e.g. pipeline or look ahead using a secondary processor, e.g. coprocessor for non-native instruction execution, e.g. executing a command; for Java instruction set

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Microcomputers (AREA)
  • Communication Control (AREA)
FI961039A 1996-03-06 1996-03-06 Demultiplekserin rekisteriosoitus FI104392B (fi)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FI961039A FI104392B (fi) 1996-03-06 1996-03-06 Demultiplekserin rekisteriosoitus
EP97102622A EP0794486A3 (de) 1996-03-06 1997-02-19 Registeradressierung für einen Demultiplexer

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FI961039 1996-03-06
FI961039A FI104392B (fi) 1996-03-06 1996-03-06 Demultiplekserin rekisteriosoitus

Publications (3)

Publication Number Publication Date
FI961039A0 FI961039A0 (fi) 1996-03-06
FI961039L FI961039L (fi) 1997-09-07
FI104392B true FI104392B (fi) 2000-01-14

Family

ID=8545593

Family Applications (1)

Application Number Title Priority Date Filing Date
FI961039A FI104392B (fi) 1996-03-06 1996-03-06 Demultiplekserin rekisteriosoitus

Country Status (2)

Country Link
EP (1) EP0794486A3 (de)
FI (1) FI104392B (de)

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4070703A (en) * 1976-09-27 1978-01-24 Honeywell Information Systems Inc. Control store organization in a microprogrammed data processing system
US4318175A (en) * 1979-08-13 1982-03-02 Bunker Ramo Corporation Addressing means for random access memory system
US4849875A (en) * 1987-03-03 1989-07-18 Tandon Corporation Computer address modification system with optional DMA paging
US5280599A (en) * 1989-01-09 1994-01-18 Kabushiki Kaisha Toshiba Computer system with memory expansion function and expansion memory setting method
US5396606A (en) * 1991-07-31 1995-03-07 Franklin Electronic Publishers, Incorporated Address bus switching between sequential and non-sequential ROM searches
US5737748A (en) * 1995-03-15 1998-04-07 Texas Instruments Incorporated Microprocessor unit having a first level write-through cache memory and a smaller second-level write-back cache memory

Also Published As

Publication number Publication date
EP0794486A2 (de) 1997-09-10
FI961039A0 (fi) 1996-03-06
EP0794486A3 (de) 2001-04-04
FI961039L (fi) 1997-09-07

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