ES485894A1 - Disposicion para la generacion de senales de control de ca- dencia en una instalacion de tratamiento digital que trabajasincronicamente - Google Patents

Disposicion para la generacion de senales de control de ca- dencia en una instalacion de tratamiento digital que trabajasincronicamente

Info

Publication number
ES485894A1
ES485894A1 ES485894A ES485894A ES485894A1 ES 485894 A1 ES485894 A1 ES 485894A1 ES 485894 A ES485894 A ES 485894A ES 485894 A ES485894 A ES 485894A ES 485894 A1 ES485894 A1 ES 485894A1
Authority
ES
Spain
Prior art keywords
rings
timing signals
ring
micro instruction
master clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES485894A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of ES485894A1 publication Critical patent/ES485894A1/es
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microcomputers (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

Disposición para la generación de señales de control de cadencia en una instalación de tratamiento digital que trabaja sincrónicamente, que consta de varias plaquitas de circuito, caracterizada porque varias o todas las plaquitas de circuito tienen una disposición (anillo-T) para la generación de señales de tiempo, y porque todos los anillos-T trabajan sincrónicamente unos con respecto a los otros.
ES485894A 1978-12-12 1979-11-13 Disposicion para la generacion de senales de control de ca- dencia en una instalacion de tratamiento digital que trabajasincronicamente Expired ES485894A1 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE2853523A DE2853523C2 (de) 1978-12-12 1978-12-12 Dezentrale Erzeugung von Taktsteuersignalen

Publications (1)

Publication Number Publication Date
ES485894A1 true ES485894A1 (es) 1980-05-16

Family

ID=6056893

Family Applications (1)

Application Number Title Priority Date Filing Date
ES485894A Expired ES485894A1 (es) 1978-12-12 1979-11-13 Disposicion para la generacion de senales de control de ca- dencia en una instalacion de tratamiento digital que trabajasincronicamente

Country Status (9)

Country Link
US (1) US4419739A (es)
EP (1) EP0012186B1 (es)
JP (1) JPS6029402B2 (es)
AU (1) AU526728B2 (es)
BR (1) BR7908072A (es)
CA (1) CA1139000A (es)
DE (2) DE2853523C2 (es)
ES (1) ES485894A1 (es)
IT (1) IT1164524B (es)

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US4503490A (en) * 1981-06-10 1985-03-05 At&T Bell Laboratories Distributed timing system
JPS57212690A (en) * 1981-06-24 1982-12-27 Hitachi Ltd Dynamic mos memory device
JPS581889A (ja) * 1981-06-29 1983-01-07 Fujitsu Ltd 半導体記憶装置のダミ−セル制御方式
US4482819A (en) * 1982-01-25 1984-11-13 International Business Machines Corporation Data processor system clock checking system
US4494223B1 (en) * 1982-09-16 1999-09-07 Texas Instruments Inc Sequentially clocked substrate bias generator for dynamic memory
US4551836A (en) * 1983-06-22 1985-11-05 Gte Automatic Electric Incorporated Cross-copy arrangement for synchronizing error detection clock signals in a duplex digital system
US4725944A (en) * 1983-11-14 1988-02-16 Tandem Computers Incorporated Electronic communication clocking mechanism
US4575848A (en) * 1984-02-01 1986-03-11 Westinghouse Electric Corp. Methods and apparatus for correcting a software clock from an accurate clock
JPS6227813A (ja) * 1985-07-29 1987-02-05 Hitachi Ltd 位相同期方式
US4714924A (en) * 1985-12-30 1987-12-22 Eta Systems, Inc. Electronic clock tuning system
DE3609715A1 (de) * 1986-03-21 1987-10-01 Siemens Ag Taktgenerator mit mehreren taktphasen zur erzeugung von gleichstromimpulsen mit extern steuerbaren muttertaktabhaengigen periodenlaengen
US4763318A (en) * 1986-05-02 1988-08-09 Datos Corporation Transmission and reception of synchronous data and timing signals using a steady bit stream
US4769558A (en) * 1986-07-09 1988-09-06 Eta Systems, Inc. Integrated circuit clock bus layout delay system
US5140688A (en) * 1986-11-10 1992-08-18 Texas Instruments Incorporated GaAs integrated circuit programmable delay line element
US5184027A (en) * 1987-03-20 1993-02-02 Hitachi, Ltd. Clock signal supply system
DE3870680D1 (de) * 1987-03-20 1992-06-11 Hitachi Ltd Taktsignal-versorgungssystem.
US4794275A (en) * 1987-09-17 1988-12-27 Tektronix, Inc. Multiple phase clock generator
US4864574A (en) * 1988-02-04 1989-09-05 Rockwell International Corporation Injection lock clock detection apparatus
US5428754A (en) * 1988-03-23 1995-06-27 3Dlabs Ltd Computer system with clock shared between processors executing separate instruction streams
US5537602A (en) * 1988-09-16 1996-07-16 Hitachi, Ltd. Process system for controlling bus system to communicate data between resource and processor
US5367662A (en) * 1988-09-16 1994-11-22 Hitachi, Ltd. Distributed machine state controlled processor system with a CPU clocked with a reference signal delayed from a system clock
US5062041A (en) * 1988-12-29 1991-10-29 Wang Laboratories, Inc. Processor/coprocessor interface apparatus including microinstruction clock synchronization
EP0461291A1 (en) * 1990-06-15 1991-12-18 International Business Machines Corporation Clock generation in a multi-chip computersystem
US5212443A (en) * 1990-09-05 1993-05-18 Schlumberger Technologies, Inc. Event sequencer for automatic test equipment
US5225772A (en) * 1990-09-05 1993-07-06 Schlumberger Technologies, Inc. Automatic test equipment system using pin slice architecture
EP0520675A3 (en) * 1991-06-28 1993-03-17 Sgs-Thomson Microelectronics, Inc. Flushable delay line
US5812832A (en) * 1993-01-29 1998-09-22 Advanced Micro Devices, Inc. Digital clock waveform generator and method for generating a clock signal
US5553276A (en) * 1993-06-30 1996-09-03 International Business Machines Corporation Self-time processor with dynamic clock generator having plurality of tracking elements for outputting sequencing signals to functional units
US5418934A (en) * 1993-09-30 1995-05-23 Intel Corporation Synchronizing chained distributed digital chronometers by the use of an echo signal
US6064707A (en) 1995-12-22 2000-05-16 Zilog, Inc. Apparatus and method for data synchronizing and tracking
US6434640B1 (en) 1999-05-25 2002-08-13 Advanced Micro Devices, Inc. Unload counter adjust logic for a receiver buffer
US6370600B1 (en) 1999-05-25 2002-04-09 Advanced Micro Devices, Inc. Staging buffer for translating clock domains when source clock frequency exceeds target clock frequency
US6424688B1 (en) 1999-10-27 2002-07-23 Advanced Micro Devices, Inc. Method to transfer data in a system with multiple clock domains using clock skipping techniques
US6711696B1 (en) 2000-08-11 2004-03-23 Advanced Micro Devices, Inc. Method for transfering data between two different clock domains by calculating which pulses of the faster clock domain should be skipped substantially simultaneously with the transfer
US6748039B1 (en) 2000-08-11 2004-06-08 Advanced Micro Devices, Inc. System and method for synchronizing a skip pattern and initializing a clock forwarding interface in a multiple-clock system
US6573757B1 (en) 2000-09-11 2003-06-03 Cypress Semiconductor Corp. Signal line matching technique for ICS/PCBS
US6494785B1 (en) 2000-10-11 2002-12-17 Igt Gaming device having a destination pursuit bonus scheme with advance and setback conditions
US6659864B2 (en) 2000-10-12 2003-12-09 Igt Gaming device having an unveiling award mechanical secondary display
US6952791B2 (en) * 2001-12-03 2005-10-04 Broadcom Corporation Method and circuit for initializing a de-skewing buffer in a clock forwarded system
US8295182B2 (en) * 2007-07-03 2012-10-23 Credence Systems Corporation Routed event test system and method

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1099495A (en) * 1964-04-29 1968-01-17 Int Computers & Tabulators Ltd Improvements in or relating to clock pulse distribution
US3351918A (en) * 1965-02-15 1967-11-07 Rca Corp Computer system employing specialized instruction execution units
US3566364A (en) * 1968-07-19 1971-02-23 Burroughs Corp Data processor having operator family controllers
US3656123A (en) * 1970-04-16 1972-04-11 Ibm Microprogrammed processor with variable basic machine cycle lengths
US3725793A (en) * 1971-12-15 1973-04-03 Bell Telephone Labor Inc Clock synchronization arrangement employing delay devices
US3919695A (en) * 1973-12-26 1975-11-11 Ibm Asynchronous clocking apparatus
US4037090A (en) * 1974-11-19 1977-07-19 Texas Instruments Incorporated Multiphase clocking for MOS
GB1561961A (en) * 1977-04-20 1980-03-05 Int Computers Ltd Data processing units
US4241418A (en) * 1977-11-23 1980-12-23 Honeywell Information Systems Inc. Clock system having a dynamically selectable clock period
DE2853546C2 (de) * 1978-12-12 1982-02-25 Ibm Deutschland Gmbh, 7000 Stuttgart Prüfschaltung für mindestens zwei synchron arbeitende Taktgeber
US4254475A (en) * 1979-03-12 1981-03-03 Raytheon Company Microprocessor having dual frequency clock
US4338677A (en) * 1980-06-17 1982-07-06 Hewlett-Packard Company Multi-clock data capture circuit

Also Published As

Publication number Publication date
DE2853523A1 (de) 1980-06-19
IT7927741A0 (it) 1979-11-30
AU526728B2 (en) 1983-01-27
EP0012186B1 (de) 1983-04-13
JPS6029402B2 (ja) 1985-07-10
JPS5580137A (en) 1980-06-17
EP0012186A1 (de) 1980-06-25
CA1139000A (en) 1983-01-04
IT1164524B (it) 1987-04-15
DE2853523C2 (de) 1981-10-01
AU5355379A (en) 1980-06-19
BR7908072A (pt) 1980-07-22
DE2965213D1 (en) 1983-05-19
US4419739A (en) 1983-12-06

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