ES467326A1 - Un controlador de linea general de canales en un sistema de tratamiento de datos. - Google Patents

Un controlador de linea general de canales en un sistema de tratamiento de datos.

Info

Publication number
ES467326A1
ES467326A1 ES467326A ES467326A ES467326A1 ES 467326 A1 ES467326 A1 ES 467326A1 ES 467326 A ES467326 A ES 467326A ES 467326 A ES467326 A ES 467326A ES 467326 A1 ES467326 A1 ES 467326A1
Authority
ES
Spain
Prior art keywords
request
channel
storage
cbc
group
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES467326A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of ES467326A1 publication Critical patent/ES467326A1/es
Expired legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10Program control for peripheral devices
    • G06F13/12Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/122Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Calculators And Similar Devices (AREA)
  • Microcomputers (AREA)
  • Communication Control (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
ES467326A 1977-03-28 1978-02-25 Un controlador de linea general de canales en un sistema de tratamiento de datos. Expired ES467326A1 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/781,895 US4115854A (en) 1977-03-28 1977-03-28 Channel bus controller

Publications (1)

Publication Number Publication Date
ES467326A1 true ES467326A1 (es) 1978-11-01

Family

ID=25124299

Family Applications (1)

Application Number Title Priority Date Filing Date
ES467326A Expired ES467326A1 (es) 1977-03-28 1978-02-25 Un controlador de linea general de canales en un sistema de tratamiento de datos.

Country Status (12)

Country Link
US (1) US4115854A (es)
JP (1) JPS53120240A (es)
AU (1) AU515256B2 (es)
BR (1) BR7801871A (es)
CA (1) CA1089107A (es)
CH (1) CH626735A5 (es)
DE (1) DE2809602C3 (es)
ES (1) ES467326A1 (es)
FR (1) FR2386075A1 (es)
GB (1) GB1568474A (es)
IT (1) IT1109990B (es)
PH (1) PH13850A (es)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4126897A (en) * 1977-07-05 1978-11-21 International Business Machines Corporation Request forwarding system
JPS586173B2 (ja) * 1978-01-20 1983-02-03 株式会社日立製作所 チャネル制御方式
US4268906A (en) * 1978-12-22 1981-05-19 International Business Machines Corporation Data processor input/output controller
US4320456A (en) * 1980-01-18 1982-03-16 International Business Machines Corporation Control apparatus for virtual address translation unit
US4435762A (en) 1981-03-06 1984-03-06 International Business Machines Corporation Buffered peripheral subsystems
US4472787A (en) * 1981-08-12 1984-09-18 Rockwell International Corporation System for transferring words on a bus with capability to intermix first attempts and retrys
US4503501A (en) * 1981-11-27 1985-03-05 Storage Technology Corporation Adaptive domain partitioning of cache memory space
DE3241402A1 (de) * 1982-11-09 1984-05-10 Siemens AG, 1000 Berlin und 8000 München Verfahren zum steuern des datentransfers zwischen einem datensender und einem datenempfaenger ueber einen bus mit hilfe einer am bus angeschlossenen steuereinrichtung
US4604709A (en) * 1983-02-14 1986-08-05 International Business Machines Corp. Channel communicator
US4604689A (en) * 1983-04-15 1986-08-05 Convergent Technologies, Inc. Bus repeater
JPS60229160A (ja) * 1984-04-26 1985-11-14 Toshiba Corp マルチプロセツサシステム
CA1228677A (en) * 1984-06-21 1987-10-27 Cray Research, Inc. Peripheral interface system
US4858116A (en) * 1987-05-01 1989-08-15 Digital Equipment Corporation Method and apparatus for managing multiple lock indicators in a multiprocessor computer system
US4949239A (en) * 1987-05-01 1990-08-14 Digital Equipment Corporation System for implementing multiple lock indicators on synchronous pended bus in multiprocessor computer system
US5341510A (en) * 1987-05-01 1994-08-23 Digital Equipment Corporation Commander node method and apparatus for assuring adequate access to system resources in a multiprocessor
US5101477A (en) * 1990-02-16 1992-03-31 International Business Machines Corp. System for high speed transfer of data frames between a channel and an input/output device with request and backup request count registers
US5398330A (en) * 1992-03-05 1995-03-14 Seiko Epson Corporation Register file backup queue
US5666551A (en) * 1994-06-30 1997-09-09 Digital Equipment Corporation Distributed data bus sequencing for a system bus with separate address and data bus protocols
US6108734A (en) * 1997-12-01 2000-08-22 Digital Equipment Corporation Method and apparatus for a relaxed bus protocol using heuristics and higher level supervision
US6542971B1 (en) * 2001-04-23 2003-04-01 Nvidia Corporation Memory access system and method employing an auxiliary buffer
US7885405B1 (en) * 2004-06-04 2011-02-08 GlobalFoundries, Inc. Multi-gigabit per second concurrent encryption in block cipher modes
US7913024B2 (en) * 2008-12-09 2011-03-22 International Business Machines Corporation Differentiating traffic types in a multi-root PCI express environment
US8144582B2 (en) * 2008-12-30 2012-03-27 International Business Machines Corporation Differentiating blade destination and traffic types in a multi-root PCIe environment
CN113434355B (zh) 2021-08-26 2021-12-17 苏州浪潮智能科技有限公司 模块验证方法、uvm验证平台、电子设备及存储介质

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1483564A (es) * 1965-06-18 1967-09-06
US3702462A (en) * 1967-10-26 1972-11-07 Delaware Sds Inc Computer input-output system
DE1774183A1 (de) * 1968-04-26 1972-03-09 Siemens Ag Verfahren zur Zwischenspeicherung von Informationen,insbesondere in Fernsprechvermittlungsanlagen
US3699530A (en) * 1970-12-30 1972-10-17 Ibm Input/output system with dedicated channel buffering
US3976477A (en) * 1974-12-23 1976-08-24 Olin Corporation High conductivity high temperature copper alloy
US4017839A (en) * 1975-06-30 1977-04-12 Honeywell Information Systems, Inc. Input/output multiplexer security system

Also Published As

Publication number Publication date
FR2386075B1 (es) 1981-02-06
IT7821591A0 (it) 1978-03-24
GB1568474A (en) 1980-05-29
DE2809602B2 (de) 1979-05-31
CA1089107A (en) 1980-11-04
AU515256B2 (en) 1981-03-26
PH13850A (en) 1980-10-22
AU3392678A (en) 1979-09-13
DE2809602C3 (de) 1980-01-31
CH626735A5 (es) 1981-11-30
IT1109990B (it) 1985-12-23
US4115854A (en) 1978-09-19
FR2386075A1 (fr) 1978-10-27
BR7801871A (pt) 1979-04-17
JPS53120240A (en) 1978-10-20
JPS5547407B2 (es) 1980-11-29
DE2809602A1 (de) 1978-10-05

Similar Documents

Publication Publication Date Title
ES467326A1 (es) Un controlador de linea general de canales en un sistema de tratamiento de datos.
US4550368A (en) High-speed memory and memory management system
US4954988A (en) Memory device wherein a shadow register corresponds to each memory cell
US4803621A (en) Memory access system
US3693165A (en) Parallel addressing of a storage hierarchy in a data processing system using virtual addressing
KR860000601A (ko) 메모리 액세스 제어 시스템
CA2245106A1 (en) Method and system for input/output control in a multiprocessor system utilizing simultaneous variable-width bus access
GB1349999A (en) Autonomous multiple-path input/output control system
GB950911A (en) Modular computer system
EP0251056A3 (en) Cache tag lookaside
EP0229932A2 (en) High-capacity memory for multiprocessor systems
GB1444592A (en) Memory arrnagmeents for data processing apparatus
GB1336981A (en) Digital electric information processing system
ES471406A1 (es) Perfeccionamientos introducidos en un sistema de tratamientode datos
US5301292A (en) Page mode comparator decode logic for variable size DRAM types and different interleave options
US5146572A (en) Multiple data format interface
US5668975A (en) Method of requesting data by interlacing critical and non-critical data words of multiple data requests and apparatus therefor
JPH03189843A (ja) データ処理システムおよび方法
US3351913A (en) Memory system including means for selectively altering or not altering restored data
Baozhao et al. Two-dimensional image processing without transpose
KR880011663A (ko) 메모리 관리장치와 이 장치에서 사용하기 위한 방법 및 이 장치를 가지고 있는 시스템
Winsor et al. Crosspoint Cache Architectures.
GB1332031A (en) Information processing systems
US5371875A (en) Logic on main storage memory cards for insertion and extraction of tag bits
JPS57157333A (en) Memory address control system

Legal Events

Date Code Title Description
FD1A Patent lapsed

Effective date: 19981103