ES248357U - Programmable interruption controller (Machine-translation by Google Translate, not legally binding) - Google Patents

Abstract

Programmable interrupt controller, which having the purpose of generating a plurality of vector interruptions for a microprocessor, is essentially characterized by a receiver block of the address and control bus lines, associated with an address decoder and eight prom-type memories powered by consumption saving circuits, said prom memories receiving all the address lines, except a prom that includes the vectors of the plurality of interruptions, using a subset of the addressing lines to discriminate the selection of the prom memories, through a decoder block from three to eight, having provided an address changing circuit that receives and stores the possible interruption lines according to a preassigned priority and generating the corresponding interruption vector with the particularity of existing a chain of meters, in bcd code, which divides the base frequency of a clock, according to three possibilities, selectable by switch, accessing the interruptions of this clock to the circuit changed of directions as well as to "drivers" with tri-state control, through bistable circuits and existing two monostable circuits activators of corresponding led diodes in the presence of an interruption or addressing. (Machine-translation by Google Translate, not legally binding)