ES2377375B1 - INTEGRATED LINEAR RESISTANCE WITH TEMPERATURE COMPENSATION. - Google Patents

Abstract

Integrated linear resistance with temperature compensation. # It allows to provide a resistance whose resistivity is essentially constant when faced with temperature changes, providing an effective, simple, compact and fully compatible solution with CMOS technology. Said integrated linear resistance stands out mainly for understanding an MRC network; and a first control circuit comprising a current mirror formed by two MOS transistors (M {sub, 31}, M {sub, 41}) polarized by a current source (I {sub, B1}) independent of temperature and comprising a branch with two resistors (R {sub, A1}, R {sub, B1}) in series whose terminal is connected to a first group of doors (G {sub, 1}) of the MRC network; and where the value of the two resistors (R {sub, A1}, R {sub, B1}) is such that the variation of R {sub, 1} = R {sub, A1} + R {sub, B1} compensates the deviations caused by the temperature in R {sub, MRC}.

Description

INTEGRATED LINEAR RESISTANCE WITH COMPENSATION OF TEMPERATURE

OBJECTIVE OF THE INVENTION

The present invention falls within the field of microelectronic systems, and more specifically in the systems of processing and processing of analog electrical signals made in CMOS technology that require linear resistors with low thermal dependence. Specifically, the object of the present invention is to provide a resistance whose resistivity is essentially constant against changes in temperature.

BACKGROUND OF THE INVENTION

The characteristic parameters of many analog circuits are directly related to their passive components, both resistive and capacitive. For example, the gain of an amplifier can be determined by quotients of resistances and / or capacities, while the critical frequencies of a filter are given by RC products. For this reason, it is extremely important to select suitable resistors for each application, usually based on factors such as linearity, area, polarization circuit complexity or temperature resistance variation.

In standard CMOS processes, the most ideal resistors are simple polysilicon strips. However, the specific or frame resistance is small even in the case of high resistivity polysilicon. Another known drawback is that resistance deviations of up to 20% with respect to the expected value often occur due to variations in the process and high temperature coefficients. Additionally, the effect of circuit aging must be added to this. However, the major drawback of both the integrated passive resistors, such as polysilicon resistors, pit resistance N or P is that they are extremely sensitive to variations in temperature, which adds to the relatively high area of silicon required for its implementation if its corresponding resistive value is high

Another option is the use of MOS transistors as a resistive element, which not only implies considerable area savings, but also enables direct control of the resistance value through the transistor's door voltage. Whenever the parameters of a circuit are a function of the value of a resistor, it is possible to implement a fine adjustment of them by using MOS transistors in the ohmic zone. Although the use of MOS transistors solves the silicon area problem required by the integrated passive resistors, the MOS transistors are far from being immune to temperature fluctuations. In addition, another drawback of the use of MOS transistors as resistors is the limitation of the dynamic range, since the transistors have, even in this region of operation, a highly non-linear output characteristic.

The resistive MOS circuit, or MRC, shown in Fig. 1a, is a standard solution to these nonlinearity problems. Under certain polarization conditions and for a permissible range of input voltages (V1 and Vd), this circuit behaves like a highly linear resistance (see Fig. 1b) whose magnitude is controllable through the difference in voltages of control V G1, VG2, as described by Zdzislaw Czarnul in "Novel MOS Resistive Circuit for Synthesis of Fully Integrated Continous -Time Filters", IEEE Trans. Circuit Syst., vol. CAS -33, No. 7, pp. 718-721 , July 1986).

The characteristic of this circuit, assuming that the MOS transistors work in strong investment and in the triad zone is described by:

(one )

where J is the mobility of the carriers in the transistor channel, Cax is

the capacity of the gate oxide per unit area, VG1-VG2 the difference of gate voltages applied to the transistors and V1-V2 the difference of input voltages. Reordering this equation you get:

where

(3)

That is, the RMRC differential resistance of the MRC network is inversely proportional to the mobility ¡J, which introduces the main dependence of the resistive value with the temperature, as shown in Fig. 1c.

Thus, it would be desirable to provide a thermally compensated active resistance that is not only economical in terms of silicon area, but also has a high linearity and its value is controllable and independent of temperature variations.

DESCRIPTION OF THE INVENTION

The present invention proposes an effective, simple, compact and fully compatible solution with CMOS technology. The proposed integrated linear resistance is formed by an MRC network whose variations with temperature are compensated using at least one control circuit. Although the topologies defined in this application are implemented using PMOS transistors, it is understood that it would also be possible to implement them using NMOS transistors.

The parts comprising the integrated linear resistance with temperature compensation of the invention are described in greater detail below, the implementation of which with two control circuits is shown in Fig. 2a:

a) MRC network

In this document, the term "MRC network" refers to the circuit known in the art described above and which is represented in Fig. 1a, formed by four identical transistors working in a triad whose doors are connected two by two and whose Channel terminals intersect.

b) Control circuit

The control circuit of the present invention has two main functions:

Provide the VGi voltage levels that set the desired RMRC resistive value according to formula (3) above.

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Compensate for thermal variations of RMRC by means of adequate values of VGi voltages in order to obtain an RMRC essentially constant with temperature.

For this, the control circuit comprises a MOS current mirror equipped with a temperature independent source (lBi), configured to copy on an output branch, equipped with a pair of resistors (RAj, RBi), an intensity proportional to said intensity (lBi), resulting in the voltages VGi of the M RC circuit. With this topology, an adequate choice of resistors (RAi, RBi) allows to obtain VGi voltages whose variation with temperature compensates for changes in RMRC, resulting in a constant resistance.

The resistances (RAi, RBi) are implemented so that each pair of resistances (RAi, RBi) in series has thermal coefficients such that the variation of Ri = RAi + RBi compensates for temperature deviations in RMRC. That is, if RAi and RBi are resistors with different thermal coefficients T CAi and T CBi, it is possible to combine them to obtain an equivalent series resistance Ri = RAi + RBi with a thermal coefficient T Ci given by:

where! 3 = RA¡ / RBi is the quotient between the resistive values of RAi and RBi

Fig. 2b shows the variation of the differential intensity h-1 2 with the temperature of the integrated linear resistance of the invention formed by the RMC circuit plus the control circuits. It is appreciated that the resistance deviations are below 0.3%, in contrast to the 32% deviations of the RMC circuit without compensation that can be seen in Fig. 1 c.

BRIEF DESCRIPTION OF THE FIGURES

Fig. 1a shows an MRC circuit according to the prior art.

Fig. 1 b shows characteristic V-I of the MRC circuit of Fig. 1a.

Fig. 1 c shows the variation of the RMRC resistance of the MRC circuit of Fig. 1a as a function of temperature.

Fig. 2a shows a preferred embodiment of the integrated linear resistance of the invention.

Fig. 2b shows the variation of the resistance of the circuit of Fig. 2a as a function of temperature.

Fig. 3 shows an example of integrated linear resistance according to the invention comprising a single control circuit.

Fig. 4 shows another example of integrated linear resistance according to the invention.

PREFERRED EMBODIMENT OF THE INVENTION

As can be deduced from (3), using the configuration with two control circuits shown in Fig. 2 it is possible to make the RMRC resistor positive or negative according to the difference in gate voltages VG1 -VG2 positive or negative, respectively. On the other hand, if you only want the RMRC resistor to take either positive or negative values, you can do without one of the two control circuits (I B1 or IBd by directly connecting one of the G2 or G1 gates to a fixed reference voltage and independent of the temperature Vre! (within the range of the supply voltage), as shown in Fig. 3, in which the gate voltage VG2 remains constant, so that the compensation is effected by the other gate voltage V G1.

Another option if you want to implement both positive and negative RMRC resistors is the circuit of Fig. 4, where the Sup and SDOWN control signals will be of the same frequency and in counter phase. The circuit of Fig. 4 consists of a single MOS current mirror that provides an intensity 1, proportional to that of polarization lB, whose function is to properly polarize transistors M1-M2 that act as switches controlled by digital signals Sup and SDOWN , where SDOWN corresponds to the Sup denial (control by 1 bit). Connected to the drains of both transistors are the series resistance of RAi and RBi, with the resistive values and

adequate thermal coefficients to create the equivalent resistance Ri = R Ai + RBi with the desired thermal coefficient (4).

Thus, in case of wishing to implement positive resistances, we set SUP = VDD = '1', SDOWN = O = 'O', so that (VG1 -VG2l = I · R1, and vice versa in case of wishing to implement negative resistances, in which case (VG1 -VG2l = -1 R2.

Claims (5)

1. Integrated linear resistance with temperature compensation characterized in that it comprises: an MRC network; Y a first control circuit comprising a current mirror formed by two MOS transistors (M31, M41) polarized by a current source (I B1) independent of temperature and comprising a branch with two resistors (RA1, RB1) in series whose terminal is connected to a first group of doors (G1) of the MRC network, and where the value of the two resistors (RA1, RB1) is such that the variation of R1 = RA1 + RB1 compensates for the deviations caused by the temperature in RMRC.

2.

Integrated linear resistor according to claim 1, wherein the second group of doors (G2) is connected to a second control circuit the same as the first, thus being able to obtain both a positive or negative RMRC.

3.

Integrated linear resistance according to claim 1, wherein the second group of doors (G2) is connected to a reference node (Vre!), Thus being able to obtain either a positive or negative RMRC.

Four.

Integrated linear resistor according to claim 1, wherein the current mirror of the first control circuit is connected to two MOS transistors (M1, Md, which are in turn connected to the first (VG1) and the second (VGd groups of doors, and which also comprises a branch with two resistors (RA2, RB2) connected to said second group of doors (VGd.

5.

Integrated linear resistance according to any of the preceding claims, wherein the MOS transistors are chosen between PMOS transistors and NMOS transistors.