ES2377375A1 - Integrated linear resistance with temperature compensation - Google Patents
Integrated linear resistance with temperature compensation Download PDFInfo
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- ES2377375A1 ES2377375A1 ES201030916A ES201030916A ES2377375A1 ES 2377375 A1 ES2377375 A1 ES 2377375A1 ES 201030916 A ES201030916 A ES 201030916A ES 201030916 A ES201030916 A ES 201030916A ES 2377375 A1 ES2377375 A1 ES 2377375A1
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
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Abstract
Description
RESISTENCIA LINEAL INTEGRADA CON COMPENSACION DE TEMPERATURA INTEGRATED LINEAR RESISTANCE WITH COMPENSATION OF TEMPERATURE
OBJETIVO DE LA INVENCION OBJECTIVE OF THE INVENTION
La presente invencion se engloba dentro del campo de los sistemas microelectronicos, y mas concretamente en los sistemas de procesado y tratamiento de senales electricas analogicas realizados en tecnologfa CMOS que precisan de resistencias lineales con baja dependencia termica. Concretamente, el objeto de la presente invencion es proporcionar una resistencia cuya resistividad sea esencialmente constante ante cambios de temperatura. ANTECEDENTES DE LA INVENCION The present invention falls within the field of microelectronic systems, and more specifically in the analogue signal processing and treatment systems performed in CMOS technology that require linear resistance with low thermal dependence. Specifically, the object of the present invention is to provide a resistance whose resistivity is essentially constant in the face of temperature changes. BACKGROUND OF THE INVENTION
Los parametros caracterfsticos de muchos circuitos analogicos estan directamente relacionados con sus componentes pasivos, tanto resistivos como capacitivos. Por ejemplo, la ganancia de un amplificador puede estar determinada por cocientes de resistencias y/o capacidades, mientras que las frecuencias crfticas de un filtro vienen dadas por productos RC. Por ese motivo, es extremadamente importante seleccionar resistencias adecuadas a cada aplicacion, normalmente en funcion de factores como la linealidad, el area, la complejidad del circuito de polarizacion o la variacion de la resistencia con la temperatura. The characteristic parameters of many analog circuits are directly related to their passive components, both resistive and capacitive. For example, the gain of an amplifier can be determined by quotients of resistors and / or capacities, while the critical frequencies of a filter are given by RC products. For this reason, it is extremely important to select suitable resistors for each application, usually based on factors such as linearity, area, polarization circuit complexity or resistance variation with temperature.
En procesos CMOS estandares, las resistencias mas ideales son simples tiras de polisilicio. Sin embargo, la resistencia especffica o por cuadro es pequena incluso en el caso de polisilicio de alta resistividad. Otro inconveniente conocido es que con frecuencia se producen desviaciones de la resistencia de hasta un 20% respecto al valor esperado debido a variaciones en el proceso y a los elevados coeficientes de temperatura. Adicionalmente, hay que anadir a esto el efecto del envejecimiento de los circuitos. Sin embargo, el mayor inconveniente tanto de las resistencias pasivas integradas, como resistencias de polisilicio, resistencias de pozo N o P es que son extremadamente sensibles a las variaciones en la temperatura, a lo que se suma la relativamente elevada area de silicio requerida para su implementacion si su correspondiente valor resistivo es elevado In standard CMOS processes, the most ideal resistors are simple polysilicon strips. However, the specific or frame resistance is small even in the case of high resistivity polysilicon. Another known drawback is that resistance deviations of up to 20% with respect to the expected value often occur due to variations in the process and high temperature coefficients. Additionally, the effect of circuit aging must be added to this. However, the major drawback of both the integrated passive resistors, such as polysilicon resistors, pit resistance N or P is that they are extremely sensitive to variations in temperature, to which is added the relatively high area of silicon required for its implementation if its corresponding resistive value is high
Otra opcion es el uso de transistores MOS como elemento resistivo, lo cual no solo implica un considerable ahorro de area, sino que ademas posibilita el control directo del valor de la resistencia a traves de la tension de puerta del transistor. Siempre que los parametros de un circuito sean funcion del valor de una resistencia es posible implementar un ajuste fino de los mismos mediante el uso de transistores MOS en zona ohmica. Aunque el empleo de transistores MOS soluciona el problema del area de silicio requerido por las resistencias pasivas integradas, los transistores MOS distan de ser inmunes a las fluctuaciones de temperatura. Ademas, otro de los inconvenientes del empleo de transistores MOS como resistencias es la limitacion del rango dinamico, ya que los transistores presentan, incluso en esta region de operacion, una caracterfstica de salida altamente no lineal. Another option is the use of MOS transistors as a resistive element, which not only implies considerable area savings, but also enables direct control of the resistance value through the transistor's door voltage. Whenever the parameters of a circuit are a function of the value of a resistor, it is possible to implement a fine adjustment of them by using MOS transistors in the ohmic zone. Although the use of MOS transistors solves the silicon area problem required by the integrated passive resistors, the MOS transistors are far from being immune to temperature fluctuations. In addition, another of the disadvantages of using MOS transistors as resistors is the limitation of the dynamic range, since the transistors have, even in this region of operation, a highly non-linear output characteristic.
El circuito MOS resistivo, o MRC, que se muestra en la Fig. 1a, es una solucion estandar a estos problemas de no linealidad. Bajo unas determinadas condiciones de polarizacion y para un rango de permitido de tensiones de entrada (V1 y V2), este circuito se comporta como una resistencia altamente lineal (vease la Fig. 1b) cuya magnitud es controlable a traves de la diferencia de unas tensiones de control VG1, VG2, como describe Zdzislaw Czarnul en "Novel MOS Resistive Circuit for Synthesis of Fully Integrated Continous - Time Filters", IEEE Trans. Circuit Syst., vol. CAS - 33, nQ. 7, pp. 718 - 721, Julio 1986). The resistive MOS circuit, or MRC, shown in Fig. 1a, is a standard solution to these nonlinearity problems. Under certain polarization conditions and for a permissible range of input voltages (V1 and V2), this circuit behaves like a highly linear resistance (see Fig. 1b) whose magnitude is controllable through the difference of some voltages of control VG1, VG2, as described by Zdzislaw Czarnul in "Novel MOS Resistive Circuit for Synthesis of Fully Integrated Continous - Time Filters", IEEE Trans. Circuit Syst., Vol. CAS - 33, nQ. 7, pp. 718-721, July 1986).
La caracterfstica de este circuito, supuesto que los transistores MOS trabajan en inversion fuerte y en la zona de triodo esta descrita por: The characteristic of this circuit, assuming that MOS transistors work in strong investment and in the triode zone is described by:
(1) (one)
donde where
es la movilidad de los portadores en el canal del transistor, Cox es la capacidad del oxido de puerta por unidad de area, VG1-VG2 la diferencia de tensiones de puerta aplicadas a los transistores y V1-V2 la diferencia de tensiones de entrada. Reordenando esta ecuacion se obtiene: is the mobility of the carriers in the transistor channel, Cox is the capacity of the gate oxide per unit area, VG1-VG2 the difference of gate voltages applied to the transistors and V1-V2 the difference of input voltages. Reordering this equation you get:
donde where
Es decir, la resistencia diferencial RMRC de la red MRC es inversamente proporcional a la movilidad That is, the RMRC differential resistance of the MRC network is inversely proportional to mobility.
, la cual introduce la principal dependencia del valor resistivo con la temperatura, como se observa en la Fig. 1c. , which introduces the main dependence of the resistive value with temperature, as seen in Fig. 1c.
Asf pues, serfa deseable proporcionar una resistencia activa compensada termicamente que no solamente sea economica en terminos de area de silicio, sino que ademas presente una elevada linealidad y su valor sea controlable e independiente de las variaciones de la temperatura. Thus, it would be desirable to provide a thermally compensated active resistance that is not only economical in terms of silicon area, but also has a high linearity and its value is controllable and independent of temperature variations.
DESCRIPCION DE LA INVENCION DESCRIPTION OF THE INVENTION
La presente invencion propone una solucion efectiva, sencilla, compacta y completamente compatible con la tecnologfa CMOS. La resistencia lineal integrada que se propone esta formada por una red MRC cuyas variaciones con la temperatura se compensan empleando al menos un circuito de control. Aunque las topologfas definidas en esta solicitud estan implementadas utilizando transistores PMOS, se entiende que serfa posible tambien implementarlos utilizando transistores NMOS. The present invention proposes an effective, simple, compact and fully compatible solution with CMOS technology. The proposed integrated linear resistance is formed by an MRC network whose variations with temperature are compensated using at least one control circuit. Although the topologies defined in this application are implemented using PMOS transistors, it is understood that it would also be possible to implement them using NMOS transistors.
A continuacion se describen con mayor detalle las partes que componen la resistencia lineal integrada con compensacion de temperatura de la invencion, cuya implementacion con dos circuitos de control se muestra en la Fig. 2a: The parts that compose the integrated linear resistance with temperature compensation of the invention are described in greater detail below, the implementation of which with two control circuits is shown in Fig. 2a:
a) Red MRC a) MRC network
En el presente documento, el termino "red MRC" hace referencia al circuito conocido en la tecnica que se describio anteriormente y que se representa en la Fig. 1a, formado por cuatro transistores identicos trabajando en triodo cuyas puertas estan conectadas dos a dos y cuyos terminales de canal se cruzan. In this document, the term "MRC network" refers to the circuit known in the art described above and which is represented in Fig. 1a, formed by four identical transistors working in a triode whose doors are connected two by two and whose Channel terminals intersect.
b) Circuito de control b) Control circuit
El circuito de control de la presente invencion tiene dos funciones principales: The control circuit of the present invention has two main functions:
- --
- Proporcionar los niveles de tension VGi que fijan el valor resistivo RMRC deseado segun la formula (3) anterior. Provide the VGi voltage levels that set the desired RMRC resistive value according to formula (3) above.
- --
- Compensar las variaciones termicas de RMRC por medio de valores adecuados de los voltajes VGi con el objeto de obtener una RMRC esencialmente constante con la temperatura. Compensate for thermal variations of RMRC by means of adequate values of VGi voltages in order to obtain an RMRC essentially constant with temperature.
Para ello, el circuito de control comprende un espejo de corriente MOS dotado de una fuente de intensidad (IBi) independiente de la temperatura, configurado para copiar en una rama de salida, dotada de un par de resistencias (RAi, RBi), una intensidad proporcional a dicha intensidad (IBi), obteniendose como resultado los voltajes VGi del circuito MRC. Con esta topologfa, una adecuada eleccion de las resistencias (RAi, RBi) permite obtener voltajes VGi cuya variacion con la temperatura compensa los cambios en RMRC, dando como resultado una resistencia constante. For this, the control circuit comprises a MOS current mirror equipped with a temperature independent source (IBi), configured to copy on an output branch, equipped with a pair of resistors (RAi, RBi), an intensity proportional to said intensity (IBi), obtaining as a result the VGi voltages of the MRC circuit. With this topology, an adequate choice of resistors (RAi, RBi) allows to obtain VGi voltages whose variation with temperature compensates for changes in RMRC, resulting in a constant resistance.
Las resistencias (RAi, RBi) se implementan de modo que cada par de resistencias (RAi, RBi) en serie tenga unos coeficientes termicos tales que la variacion de Ri = RAi + RBi compense las desviaciones provocadas por la temperatura en RMRC. Es decir, si RAi y RBi son resistencias con diferentes coeficientes termicos TCAi y TCBi, es posible combinarlas para obtener una resistencia serie equivalente Ri = RAi+RBi con un coeficiente termico TCi dado por: The resistors (RAi, RBi) are implemented so that each pair of resistors (RAi, RBi) in series has thermal coefficients such that the variation of Ri = RAi + RBi compensates for the deviations caused by the RMRC temperature. That is, if RAi and RBi are resistors with different thermal coefficients TCAi and TCBi, it is possible to combine them to obtain an equivalent series resistance Ri = RAi + RBi with a thermal coefficient TCi given by:
( ) ()
donde where
=RAi/RBi es el cociente entre los valores resistivos de RAi y RBi = RAi / RBi is the quotient between the resistive values of RAi and RBi
La Fig. 2b muestra la variacion de la intensidad diferencial I1-I2 con la temperatura de la resistencia lineal integrada de la invencion formada por el circuito RMC mas los circuitos de control. Se aprecia que las desviaciones de la resistencia estan por debajo del 0,3%, en contraste con las desviaciones del 32% del circuito RMC sin compensacion que se aprecian en la Fig. 1c. Fig. 2b shows the variation of the differential intensity I1-I2 with the temperature of the integrated linear resistance of the invention formed by the RMC circuit plus the control circuits. It is appreciated that the resistance deviations are below 0.3%, in contrast to the 32% deviations of the RMC circuit without compensation that can be seen in Fig. 1c.
BREVE DESCRIPCION DE LAS FIGURAS BRIEF DESCRIPTION OF THE FIGURES
La Fig. 1a muestra un circuito MRC segun la tecnica anterior. Fig. 1a shows an MRC circuit according to the prior art.
La Fig. 1b muestra la caracterfstica V-I del circuito MRC de la Fig. 1a. Fig. 1b shows the characteristic V-I of the MRC circuit of Fig. 1a.
La Fig. 1c muestra la variacion de la resistencia RMRC del circuito MRC de la Fig. 1a en funcion de la temperatura. Fig. 1c shows the variation of the RMRC resistance of the MRC circuit of Fig. 1a as a function of temperature.
La Fig. 2a muestra una realizacion preferida de la resistencia lineal integrada de la invencion. Fig. 2a shows a preferred embodiment of the integrated linear resistance of the invention.
La Fig. 2b muestra la variacion de la resistencia del circuito de la Fig. 2a Fig. 2b shows the variation of the circuit resistance of Fig. 2a
en funcion de la temperatura. depending on the temperature.
La Fig. 3 muestra un ejemplo de resistencia lineal integrada segun la invencion que comprende un unico circuito de control. Fig. 3 shows an example of integrated linear resistance according to the invention comprising a single control circuit.
La Fig. muestra otro ejemplo de resistencia lineal integrada segun la invencion. Fig. Shows another example of integrated linear resistance according to the invention.
REALI�ACION PREFERIDA DE LA INVENCION PREFERRED EMBODIMENT OF THE INVENTION
Como puede deducirse de (3), utilizando la configuracion con dos circuitos de control mostrada en la Fig. 2 es posible hacer que la resistencia RMRC sea positiva o negativa segun la diferencia de tensiones de puerta VG1-VG2 sea positiva o negativa, respectivamente. Por otro lado, si unicamente interesa que la resistencia RMRC tome valores bien positivos o bien negativos, se puede prescindir de uno de los dos circuitos de control (IB1 o IB2) conectando directamente una de las puertas G2 o G1 a una tension de referencia fija e independiente de la temperatura Vref (dentro del rango de la tension de alimentacion), tal y como se muestra en la Fig. 3, en la cual la tension de puerta VG2 permanece constante, de forma que la compensacion se efectua mediante la otra tension de puerta VG1. As can be deduced from (3), using the configuration with two control circuits shown in Fig. 2 it is possible to make the RMRC resistor positive or negative according to the difference in gate voltages VG1-VG2 positive or negative, respectively. On the other hand, if only the RMRC resistor takes either positive or negative values, one of the two control circuits (IB1 or IB2) can be dispensed with by directly connecting one of the G2 or G1 gates to a fixed reference voltage and independent of the temperature Vref (within the range of the supply voltage), as shown in Fig. 3, in which the gate voltage VG2 remains constant, so that the compensation is effected by the other voltage of door VG1.
Otra opcion si se desean implementar resistencias RMRC tanto positivas como negativas es el circuito de la Fig. , donde las senales de control S�P y S�O�N seran de la misma frecuencia y en contrafase. El circuito de la Fig. consta de un unico espejo de corriente MOS que proporciona una intensidad I, proporcional a la de polarizacion IB, cuya funcion es polarizar adecuadamente los transistores M1-M2 que actuan como interruptores controlados por las senales digitales S�P y S�O�N, donde S�O�N corresponde a la negada de S�P (control mediante 1 bit). Conectadas a los drenadores de sendos transistores se encuentran la resistencia serie de RAi y RBi, con los valores resistivos y coeficientes termicos adecuados para crear la resistencia equivalente Ri = RAi + RBi con el coeficiente termico deseado ( ). Another option if you want to implement both positive and negative RMRC resistors is the circuit of Fig., Where the control signals S�P and S�O�N will be of the same frequency and in contraphase. The circuit of Fig. Consists of a single MOS current mirror that provides an intensity I, proportional to that of polarization IB, whose function is to properly polarize transistors M1-M2 that act as switches controlled by digital signals S�P and S�O�N, where S�O�N corresponds to the S�P denial (control by 1 bit). Connected to the drains of both transistors are the series resistance of RAi and RBi, with the appropriate resistive values and thermal coefficients to create the equivalent resistance Ri = RAi + RBi with the desired thermal coefficient ().
Asf, en caso de desear implementar resistencias positivas, fijamos S�P=V��=�1�, S�O�N=0=�0�, de manera que (VG1-VG2)= I�R1, y viceversa en el caso de desear implementar resistencias negativas, en cuyo caso (VG1-VG2)= -I�R2. Thus, if you want to implement positive resistance, we set S�P = V�� = �1�, S�O�N = 0 = �0�, so that (VG1-VG2) = I�R1, and vice versa in the case of wishing to implement negative resistances, in which case (VG1-VG2) = -I�R2.
Claims (6)
- --
- una red MRC; y an MRC network; Y
- --
- un primer circuito de control que comprende un espejo de corriente formado por dos transistores MOS (M31, M41) polarizados por una fuente de intensidad (IB1) independiente de la temperatura y que comprende un ramal con dos resistencias (RA1, RB1) en serie cuyo terminal esta conectado a un primer grupo de puertas (G1) de la red MRC, a first control circuit comprising a current mirror formed by two MOS transistors (M31, M41) polarized by a temperature independent source (IB1) and comprising a branch with two resistors (RA1, RB1) in series whose terminal is connected to a first group of doors (G1) of the MRC network,
- 2.2.
- Resistencia lineal integrada segun la reivindicaci6n 1, donde el segundo grupo de puertas (G2) esta conectado a un segundo circuito de control igual que el primero, pudiendo asf obtenerse una RMRC tanto positiva o como negativa. Integrated linear resistance according to claim 1, wherein the second group of doors (G2) is connected to a second control circuit like the first, thus being able to obtain both a positive or a negative RMRC.
- 3.3.
- Resistencia lineal integrada segun la reivindicaci6n 1, donde el segundo grupo de puertas (G2) esta conectado a un nodo de referencia (Vref), pudiendo asf obtenerse una RMRC bien positiva o bien negativa. Integrated linear resistance according to claim 1, wherein the second group of doors (G2) is connected to a reference node (Vref), thus being able to obtain either a positive or negative RMRC.
- 4.Four.
- Resistencia lineal integrada segun la reivindicaci6n 1, donde el espejo de corriente del primer circuito de control esta conectado a dos transistores MOS (M1, M2), los cuales estan a su vez conectados al primer (VG1) y al segundo (VG2) grupos de puertas, y que ademas comprende un ramal con dos resistencias (RA2, RB2) conectado a dicho segundo grupo de puertas (VG2). Integrated linear resistance according to claim 1, wherein the current mirror of the first control circuit is connected to two MOS transistors (M1, M2), which are in turn connected to the first (VG1) and the second (VG2) groups of doors, and also comprising a branch with two resistors (RA2, RB2) connected to said second group of doors (VG2).
- 5.5.
- Resistencia lineal integrada segun cualquiera de las reivindicaciones anteriores, donde los transistores MOS se eligen entre transistores PMOS y transistores NMOS. Integrated linear resistance according to any of the preceding claims, wherein the MOS transistors are chosen between PMOS transistors and NMOS transistors.
- Categoría Category
- 56 Documentos citados Reivindicaciones afectadas 56 Documents cited Claims Affected
- Y Y
- US 6650176 B1 (LORENZ PERRY S) 18.11.2003, todo el documento. 1-5 US 6650176 B1 (LORENZ PERRY S) 18.11.2003, the whole document. 1-5
- Y Y
- CZARNUL, Z.; "Novel MOS Resistive Circuit for Synthesis of Fully Integrated Continuous-Time Filters," Circuits and Systems, IEEE Transactions on, vol. 33, no. 7, pp. 718-721, Jul 1986; doi: 10.1109/TCS.1986.1085974 1-5 CZARNUL, Z .; "Novel MOS Resistive Circuit for Synthesis of Fully Integrated Continuous-Time Filters," Circuits and Systems, IEEE Transactions on, vol. 33, no. 7, pp. 718-721, Jul 1986; doi: 10.1109 / TCS.1986.1085974 1-5
- A TO
- US 6348832 B1 (CHIH YUE-DER) 19.02.2002, todo el documento. 1-5 US 6348832 B1 (CHIH YUE-DER) 19.02.2002, the whole document. 1-5
- Y Y
- US 2006125462 A1 (ECKSTEIN WOLFGANG) 15.06.2006, todo el documento. 1-5 US 2006 125462 A1 (ECKSTEIN WOLFGANG) 06.15.2006, the whole document. 1-5
- Y Y
- TAKAGI et al., "Generalized MRC [MOS Resistive Circuit]," Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on, vol. 1, pp. 221-224 vol.1, 9-12 Jun 1997; doi: 10.1109/ISCAS.1997.608677 1-5 TAKAGI et al., "Generalized MRC [MOS Resistive Circuit]," Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on, vol. 1, pp. 221-224 vol.1, 9-12 Jun 1997; doi: 10.1109 / ISCAS. 1997.608677 1-5
- A TO
- FR 2832819 A1 (ST MICROELECTRONICS SA) 30.05.2003, páginas 11-13; figuras. FR 2832819 A1 (ST MICROELECTRONICS SA) 05.30.2003, pages 11-13; figures.
- A TO
- US 2006197585 A1 (KIM HYOUNGRAE et al.) 07.09.2006, descripción; figuras. 1-5 US 2006197585 A1 (KIM HYOUNGRAE et al.) 07.09.2006, description; figures. 1-5
- Categoría de los documentos citados X: de particular relevancia Y: de particular relevancia combinado con otro/s de la misma categoría A: refleja el estado de la técnica O: referido a divulgación no escrita P: publicado entre la fecha de prioridad y la de presentación de la solicitud E: documento anterior, pero publicado después de la fecha de presentación de la solicitud Category of the documents cited X: of particular relevance Y: of particular relevance combined with other / s of the same category A: reflects the state of the art O: refers to unwritten disclosure P: published between the priority date and the date of priority submission of the application E: previous document, but published after the date of submission of the application
- El presente informe ha sido realizado • para todas las reivindicaciones • para las reivindicaciones nº: This report has been prepared • for all claims • for claims no:
- Fecha de realización del informe 12.03.2012 Date of realization of the report 12.03.2012
- Examinador M. P. López Sábater Página 1/4 Examiner M. P. López Sábater Page 1/4
- Novedad (Art. 6.1 LP 11/1986) Novelty (Art. 6.1 LP 11/1986)
- Reivindicaciones Reivindicaciones 1-5 SI NO Claims Claims 1-5 IF NOT
- Actividad inventiva (Art. 8.1 LP11/1986) Inventive activity (Art. 8.1 LP11 / 1986)
- Reivindicaciones Reivindicaciones 1-5 SI NO Claims Claims 1-5 IF NOT
- Documento Document
- Número Publicación o Identificación Fecha Publicación Publication or Identification Number publication date
- D01 D01
- US 6650176 B1 (LORENZ PERRY S) 18.11.2003 US 6650176 B1 (LORENZ PERRY S) 11/18/2003
- D02 D02
- CZARNUL, Z.; "Novel MOS Resistive Circuit for Synthesis of Fully Integrated Continuous-Time Filters," Circuits and Systems, IEEE Transactions on, vol. 33, no.7, pp. 718-721, Jul 1986; doi: 10.1109/TCS.1986.1085974 CZARNUL, Z .; "Novel MOS Resistive Circuit for Synthesis of Fully Integrated Continuous-Time Filters," Circuits and Systems, IEEE Transactions on, vol. 33, no.7, pp. 718-721, Jul 1986; doi: 10.1109 / TCS.1986.1085974
- D03 D03
- US 2006125462 A1 (ECKSTEIN WOLFGANG) 15.06.2006 US 2006 125462 A1 (ECKSTEIN WOLFGANG) 06.15.2006
- D04 D04
- TAKAGI et al., "Generalized MRC [MOS Resistive Circuit]," Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on, vol. 1, pp. 221-224 vol.1, 9 -12 Jun 1997; doi: 10.1109/ISCAS.1997.608677 TAKAGI et al., "Generalized MRC [MOS Resistive Circuit]," Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on, vol. 1, pp. 221-224 vol.1, 9-12 Jun 1997; doi: 10.1109 / ISCAS. 1997.608677
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| ES201030916A ES2377375B1 (en) | 2010-06-14 | 2010-06-14 | INTEGRATED LINEAR RESISTANCE WITH TEMPERATURE COMPENSATION. |
| PCT/ES2011/000200 WO2011157869A2 (en) | 2010-06-14 | 2011-06-14 | Integrated linear resistance with temperature compensation |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| ES201030916A ES2377375B1 (en) | 2010-06-14 | 2010-06-14 | INTEGRATED LINEAR RESISTANCE WITH TEMPERATURE COMPENSATION. |
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| Publication Number | Publication Date |
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| ES2377375A1 true ES2377375A1 (en) | 2012-03-27 |
| ES2377375B1 ES2377375B1 (en) | 2013-02-11 |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6348832B1 (en) * | 2000-04-17 | 2002-02-19 | Taiwan Semiconductor Manufacturing Co., Inc. | Reference current generator with small temperature dependence |
| FR2832819A1 (en) * | 2001-11-26 | 2003-05-30 | St Microelectronics Sa | Temperature compensated current source, uses three branches in a circuit forming two current mirrors to provide reference currents and switches between resistance paths to provide compensation |
| US6650176B1 (en) * | 2002-05-28 | 2003-11-18 | National Semiconductor Corporation | N-well resistor leakage cancellation |
| US20060125462A1 (en) * | 2004-12-14 | 2006-06-15 | Atmel Germany Gmbh | Power supply circuit for producing a reference current with a prescribable temperature dependence |
| US20060197585A1 (en) * | 2005-03-03 | 2006-09-07 | Hyoungrae Kim | Voltage reference generator and method of generating a reference voltage |
-
2010
- 2010-06-14 ES ES201030916A patent/ES2377375B1/en active Active
-
2011
- 2011-06-14 WO PCT/ES2011/000200 patent/WO2011157869A2/en active Application Filing
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6348832B1 (en) * | 2000-04-17 | 2002-02-19 | Taiwan Semiconductor Manufacturing Co., Inc. | Reference current generator with small temperature dependence |
| FR2832819A1 (en) * | 2001-11-26 | 2003-05-30 | St Microelectronics Sa | Temperature compensated current source, uses three branches in a circuit forming two current mirrors to provide reference currents and switches between resistance paths to provide compensation |
| US6650176B1 (en) * | 2002-05-28 | 2003-11-18 | National Semiconductor Corporation | N-well resistor leakage cancellation |
| US20060125462A1 (en) * | 2004-12-14 | 2006-06-15 | Atmel Germany Gmbh | Power supply circuit for producing a reference current with a prescribable temperature dependence |
| US20060197585A1 (en) * | 2005-03-03 | 2006-09-07 | Hyoungrae Kim | Voltage reference generator and method of generating a reference voltage |
Non-Patent Citations (2)
| Title |
|---|
| Czarnul, Z.; "Novel MOS Resistive Circuit for Synthesis of Fully Integrated Continuous-Time Filters," Circuits and Systems, IEEE Transactions on , vol.33, no.7, pp. 718- 721, Jul 1986; doi: 10.1109/TCS.1986.1085974 * |
| Takagi et al., "Generalized MRC [MOS Resistive Circuit]," Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on , vol.1, no., pp.221-224 vol.1, 9-12 Jun 1997; doi: 10.1109/ISCAS.1997.608677 * |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2011157869A3 (en) | 2012-03-15 |
| WO2011157869A2 (en) | 2011-12-22 |
| ES2377375B1 (en) | 2013-02-11 |
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