ES2160162T3 - Sistema y procedimiento para la comprobacion a base de reglas de concepcion local. - Google Patents

Sistema y procedimiento para la comprobacion a base de reglas de concepcion local.

Info

Publication number
ES2160162T3
ES2160162T3 ES95917750T ES95917750T ES2160162T3 ES 2160162 T3 ES2160162 T3 ES 2160162T3 ES 95917750 T ES95917750 T ES 95917750T ES 95917750 T ES95917750 T ES 95917750T ES 2160162 T3 ES2160162 T3 ES 2160162T3
Authority
ES
Spain
Prior art keywords
cell
verification
models
incompatible
processing unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES95917750T
Other languages
English (en)
Inventor
Allen Baisuck
Richard L Fairbank
Walter K Gowen Iii
Jon R Henricksen
William W Hoover Iii
Judith A Huckabay
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Cadence Design Systems Inc
Original Assignee
Cadence Design Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cadence Design Systems Inc filed Critical Cadence Design Systems Inc
Application granted granted Critical
Publication of ES2160162T3 publication Critical patent/ES2160162T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

UN SISTEMA PARA LA VERIFICACION BASADA EN UN MODELO DE REGLAS DE DISEÑO LOCALES COMPRENDE UNA UNIDAD DE PROCESAMIENTO, UNA BASE DE DATOS DE VERIFICACION EN LA QUE ESTA GRABADO UN GRAFICO DE REFERENCIA DE UNA CELDA QUE REPRESENTA UN DISEÑO DE UN CIRCUITO INTEGRADO COMO UNA COLECCION JERARQUICA DE CELDAS, UNA MEMORIA CON FUNCION DE VERIFICACION EN LA QUE ESTA GRABADA UNA FUNCION DE VERIFICACION, Y UNA MEMORIA DE CAPAS DE TRABAJO COMPATIBLE Y OTRA INCOMPATIBLE. CADA CELDA PUEDE INCLUIR MODELOS DE FORMA Y REFERENCIAS PARA CELDAS DE NIVEL INFERIOR. LA UNIDAD DE PROCESAMIENTO PRIMERO VERIFICA CADA CELDA EN EL GRAFICO DE REFERENCIA EL CUAL NO HACE REFERENCIA A NINGUNA CELDA DE NIVEL INFERIOR, DESPUES DE LO CUAL LA UNIDAD DE PROCESAMIENTO VERIFICA CADA CELDA PARA LO QUE TODA LAS CELDAS REFERENCIADAS HAN SIDO VERIFICADAS PREVIAMENTE. DURANTE LA VERIFICACION DE UNA CELDA SELECCIONADA, LA UNIDAD DE PROCESAMIENTO DETERMINA SI LOS MODELOS EN LA CELDA SELECCIONADA INTERACTUAN CON OTROS MODELOS EN LA CELDA SELECCIONADA O CON OTRA CELDA DE NIVEL INFERIOR. LOS MODELOS INTERACTIVOS ESTAN REFERIDOS COMO "INCOMPATIBLES", Y LOS MODELOS NO INTERACTIVOS ESTAN REFERIDOS COMO "COMPATIBLES". LA UNIDAD DE PROCESAMIENTO HACE REFERENCIA AL RESULTADO DE LA VERIFICACION CALCULADO PREVIAMENTE CUANDO LOS MODELOS SON COMPATIBLES, Y APLICA UNA FUNCION DE VERIFICACION A LOS MODELOS QUE SON INCOMPATIBLES. UN METODO PARA LA VERIFICACION BASADA EN UN MODELO DE REGLAS DE DISEÑO LOCALES COMPRENDE LOS SIGUIENTES PASOS: SELECCIONAR UNA CELDA PARA SU VERIFICACION; SELECCIONAR UNA FUNCION DE VERIFICACION; DETERMINAR SI LOS MODELOS EN EL GRAFICO DE REFERENCIA DE LA CELDA SON INCOMPATIBLES CON UN MODELO EN LA CELDA SELECCIONADA; APLICAR LA FUNCION DE VERIFICACION SELECCIONADA A CADA MODELO INMERSO EN UNA INTERACCION INCOMPATIBLE; Y GENERAR UNA ANULACION EN EL CASO DE QUE EL RESULTADO DE UNA VERIFICACION CALCULADA PREVIAMENTE NO SEA VALIDO A CAUSA DE LA INCOMPATIBILIDAD ENTRE LOS MODELOS.
ES95917750T 1994-04-28 1995-04-28 Sistema y procedimiento para la comprobacion a base de reglas de concepcion local. Expired - Lifetime ES2160162T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/234,410 US5559718A (en) 1994-04-28 1994-04-28 System and method for model-based verification of local design rules

Publications (1)

Publication Number Publication Date
ES2160162T3 true ES2160162T3 (es) 2001-11-01

Family

ID=22881273

Family Applications (1)

Application Number Title Priority Date Filing Date
ES95917750T Expired - Lifetime ES2160162T3 (es) 1994-04-28 1995-04-28 Sistema y procedimiento para la comprobacion a base de reglas de concepcion local.

Country Status (6)

Country Link
US (1) US5559718A (es)
EP (1) EP0757819B1 (es)
AU (1) AU2369395A (es)
DE (1) DE69521507T2 (es)
ES (1) ES2160162T3 (es)
WO (1) WO1995030198A1 (es)

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US6470477B1 (en) * 1999-12-23 2002-10-22 Koninklijke Philips Electronics N.V. Methods for converting features to a uniform micron technology in an integrated circuit design and apparatus for doing the same
US6711730B2 (en) 2002-05-13 2004-03-23 Hewlett-Packard Development Company, L.P. Synthesizing signal net information from multiple integrated circuit package models
US6922822B2 (en) * 2002-07-19 2005-07-26 Hewlett-Packard Development Company, L.P. Verifying proximity of ground vias to signal vias in an integrated circuit
US6769102B2 (en) * 2002-07-19 2004-07-27 Hewlett-Packard Development Company Verifying proximity of ground metal to signal traces in an integrated circuit
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Also Published As

Publication number Publication date
WO1995030198A1 (en) 1995-11-09
DE69521507D1 (de) 2001-08-02
EP0757819A1 (en) 1997-02-12
EP0757819B1 (en) 2001-06-27
AU2369395A (en) 1995-11-29
US5559718A (en) 1996-09-24
DE69521507T2 (de) 2001-10-11

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