ES2160162T3 - Sistema y procedimiento para la comprobacion a base de reglas de concepcion local. - Google Patents

Sistema y procedimiento para la comprobacion a base de reglas de concepcion local.

Info

Publication number
ES2160162T3
ES2160162T3 ES95917750T ES95917750T ES2160162T3 ES 2160162 T3 ES2160162 T3 ES 2160162T3 ES 95917750 T ES95917750 T ES 95917750T ES 95917750 T ES95917750 T ES 95917750T ES 2160162 T3 ES2160162 T3 ES 2160162T3
Authority
ES
Spain
Prior art keywords
cell
verification
models
incompatible
processing unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES95917750T
Other languages
English (en)
Inventor
Allen Baisuck
Richard L Fairbank
Walter K Gowen Iii
Jon R Henricksen
William W Hoover Iii
Judith A Huckabay
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Cadence Design Systems Inc
Original Assignee
Cadence Design Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cadence Design Systems Inc filed Critical Cadence Design Systems Inc
Application granted granted Critical
Publication of ES2160162T3 publication Critical patent/ES2160162T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

UN SISTEMA PARA LA VERIFICACION BASADA EN UN MODELO DE REGLAS DE DISEÑO LOCALES COMPRENDE UNA UNIDAD DE PROCESAMIENTO, UNA BASE DE DATOS DE VERIFICACION EN LA QUE ESTA GRABADO UN GRAFICO DE REFERENCIA DE UNA CELDA QUE REPRESENTA UN DISEÑO DE UN CIRCUITO INTEGRADO COMO UNA COLECCION JERARQUICA DE CELDAS, UNA MEMORIA CON FUNCION DE VERIFICACION EN LA QUE ESTA GRABADA UNA FUNCION DE VERIFICACION, Y UNA MEMORIA DE CAPAS DE TRABAJO COMPATIBLE Y OTRA INCOMPATIBLE. CADA CELDA PUEDE INCLUIR MODELOS DE FORMA Y REFERENCIAS PARA CELDAS DE NIVEL INFERIOR. LA UNIDAD DE PROCESAMIENTO PRIMERO VERIFICA CADA CELDA EN EL GRAFICO DE REFERENCIA EL CUAL NO HACE REFERENCIA A NINGUNA CELDA DE NIVEL INFERIOR, DESPUES DE LO CUAL LA UNIDAD DE PROCESAMIENTO VERIFICA CADA CELDA PARA LO QUE TODA LAS CELDAS REFERENCIADAS HAN SIDO VERIFICADAS PREVIAMENTE. DURANTE LA VERIFICACION DE UNA CELDA SELECCIONADA, LA UNIDAD DE PROCESAMIENTO DETERMINA SI LOS MODELOS EN LA CELDA SELECCIONADA INTERACTUAN CON OTROS MODELOS EN LA CELDA SELECCIONADA O CON OTRA CELDA DE NIVEL INFERIOR. LOS MODELOS INTERACTIVOS ESTAN REFERIDOS COMO "INCOMPATIBLES", Y LOS MODELOS NO INTERACTIVOS ESTAN REFERIDOS COMO "COMPATIBLES". LA UNIDAD DE PROCESAMIENTO HACE REFERENCIA AL RESULTADO DE LA VERIFICACION CALCULADO PREVIAMENTE CUANDO LOS MODELOS SON COMPATIBLES, Y APLICA UNA FUNCION DE VERIFICACION A LOS MODELOS QUE SON INCOMPATIBLES. UN METODO PARA LA VERIFICACION BASADA EN UN MODELO DE REGLAS DE DISEÑO LOCALES COMPRENDE LOS SIGUIENTES PASOS: SELECCIONAR UNA CELDA PARA SU VERIFICACION; SELECCIONAR UNA FUNCION DE VERIFICACION; DETERMINAR SI LOS MODELOS EN EL GRAFICO DE REFERENCIA DE LA CELDA SON INCOMPATIBLES CON UN MODELO EN LA CELDA SELECCIONADA; APLICAR LA FUNCION DE VERIFICACION SELECCIONADA A CADA MODELO INMERSO EN UNA INTERACCION INCOMPATIBLE; Y GENERAR UNA ANULACION EN EL CASO DE QUE EL RESULTADO DE UNA VERIFICACION CALCULADA PREVIAMENTE NO SEA VALIDO A CAUSA DE LA INCOMPATIBILIDAD ENTRE LOS MODELOS.
ES95917750T 1994-04-28 1995-04-28 Sistema y procedimiento para la comprobacion a base de reglas de concepcion local. Expired - Lifetime ES2160162T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/234,410 US5559718A (en) 1994-04-28 1994-04-28 System and method for model-based verification of local design rules

Publications (1)

Publication Number Publication Date
ES2160162T3 true ES2160162T3 (es) 2001-11-01

Family

ID=22881273

Family Applications (1)

Application Number Title Priority Date Filing Date
ES95917750T Expired - Lifetime ES2160162T3 (es) 1994-04-28 1995-04-28 Sistema y procedimiento para la comprobacion a base de reglas de concepcion local.

Country Status (6)

Country Link
US (1) US5559718A (es)
EP (1) EP0757819B1 (es)
AU (1) AU2369395A (es)
DE (1) DE69521507T2 (es)
ES (1) ES2160162T3 (es)
WO (1) WO1995030198A1 (es)

Families Citing this family (36)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5625564A (en) * 1995-01-13 1997-04-29 Cadence Design Systems, Inc. System and method for hierarchical device extraction
US6053948A (en) * 1995-06-07 2000-04-25 Synopsys, Inc. Method and apparatus using a memory model
US5844818A (en) * 1996-05-10 1998-12-01 Lsi Logic Corporation Method for creating and using design shells for integrated circuit designs
US5896300A (en) 1996-08-30 1999-04-20 Avant| Corporation Methods, apparatus and computer program products for performing post-layout verification of microelectronic circuits by filtering timing error bounds for layout critical nets
US5987240A (en) * 1996-10-29 1999-11-16 International Business Machines Corporation Design rules checker for an integrated circuit design
US6374200B1 (en) * 1997-02-03 2002-04-16 Fujitsu Limited Layout apparatus for laying out objects in space and method thereof
US6071316A (en) * 1997-09-29 2000-06-06 Honeywell Inc. Automated validation and verification of computer software
US6097887A (en) 1997-10-27 2000-08-01 Kla-Tencor Corporation Software system and method for graphically building customized recipe flowcharts
PL331114A1 (en) 1998-01-28 1999-08-02 Chipworks Method of analysing an integrated circuit, method of visualising an integrated circuit and method of analysing at last a portion of integrated circuit
US6009252A (en) * 1998-03-05 1999-12-28 Avant! Corporation Methods, apparatus and computer program products for determining equivalencies between integrated circuit schematics and layouts using color symmetrizing matrices
US6175815B1 (en) * 1998-03-12 2001-01-16 Hughes Electronics Corporation Storage reduction method for fast multipole field calculations
WO2001018695A2 (de) * 1999-09-03 2001-03-15 Infineon Technologies Ag Verfahren zum vergleich von maskendaten integrierter schaltungen mit hilfe eines rechners
US6470477B1 (en) * 1999-12-23 2002-10-22 Koninklijke Philips Electronics N.V. Methods for converting features to a uniform micron technology in an integrated circuit design and apparatus for doing the same
US6711730B2 (en) 2002-05-13 2004-03-23 Hewlett-Packard Development Company, L.P. Synthesizing signal net information from multiple integrated circuit package models
US6769102B2 (en) * 2002-07-19 2004-07-27 Hewlett-Packard Development Company Verifying proximity of ground metal to signal traces in an integrated circuit
US6922822B2 (en) * 2002-07-19 2005-07-26 Hewlett-Packard Development Company, L.P. Verifying proximity of ground vias to signal vias in an integrated circuit
US6807657B2 (en) 2002-07-19 2004-10-19 Hewlett-Packard Development Company, L.P. Inter-signal proximity verification in an integrated circuit
US6952690B2 (en) * 2002-08-22 2005-10-04 International Business Machines Corporation Loop detection in rule-based expert systems
US7047511B2 (en) * 2003-09-26 2006-05-16 International Business Machines Corporation Electronic circuit design
EP1548619A3 (en) * 2003-12-22 2009-05-13 International Business Machines Corporation Method and device for automated layer generation for double-gate finFET designs
US7448012B1 (en) 2004-04-21 2008-11-04 Qi-De Qian Methods and system for improving integrated circuit layout
US7913206B1 (en) 2004-09-16 2011-03-22 Cadence Design Systems, Inc. Method and mechanism for performing partitioning of DRC operations
JP2006285572A (ja) * 2005-03-31 2006-10-19 Toshiba Corp 半導体集積回路のレイアウト方法
US7475376B2 (en) * 2005-06-06 2009-01-06 Qimonda Ag Method and system for performing non-local geometric operations for the layout design of a semiconductor device
US20070011637A1 (en) * 2005-06-06 2007-01-11 Alexander Seidl Method and system for performing local geometrical operation on a hierarchical layout of a semiconductor device
US7904852B1 (en) 2005-09-12 2011-03-08 Cadence Design Systems, Inc. Method and system for implementing parallel processing of electronic design automation tools
US8448096B1 (en) * 2006-06-30 2013-05-21 Cadence Design Systems, Inc. Method and system for parallel processing of IC design layouts
US7707528B1 (en) * 2007-02-24 2010-04-27 Cadence Design Systems, Inc. System and method for performing verification based upon both rules and models
US7689948B1 (en) 2007-02-24 2010-03-30 Cadence Design Systems, Inc. System and method for model-based scoring and yield prediction
US7725845B1 (en) 2007-02-24 2010-05-25 Cadence Design Systems, Inc. System and method for layout optimization using model-based verification
US8214775B2 (en) 2007-09-14 2012-07-03 Luminescent Technologies, Inc. System for determining repetitive work units
KR101204676B1 (ko) 2011-02-15 2012-11-26 에스케이하이닉스 주식회사 포토마스크의 모델 기반 검증 수행 방법
US10474781B2 (en) 2014-05-24 2019-11-12 Synopsys, Inc. Virtual hierarchical layer usage
CN104268931A (zh) * 2014-09-11 2015-01-07 上海大学 基于网格模型内部结构可控装配方法
US10936778B2 (en) * 2016-03-28 2021-03-02 Motivo, Inc. And optimization of physical cell placement
US11043823B2 (en) * 2017-04-06 2021-06-22 Tesla, Inc. System and method for facilitating conditioning and testing of rechargeable battery cells

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4306286A (en) * 1979-06-29 1981-12-15 International Business Machines Corporation Logic simulation machine
EP0099114B1 (en) * 1982-07-13 1988-05-11 Nec Corporation Logic simulator operable on level basis and on logic block basis on each level
US4635218A (en) * 1983-05-09 1987-01-06 Valid Logic Systems Method for simulating system operation of static and dynamic circuit devices
JPH065541B2 (ja) * 1983-12-30 1994-01-19 株式会社日立製作所 論理回路の自動設計方法
US4703435A (en) * 1984-07-16 1987-10-27 International Business Machines Corporation Logic Synthesizer
US5050091A (en) * 1985-02-28 1991-09-17 Electric Editor, Inc. Integrated electric design system with automatic constraint satisfaction
JPS62251843A (ja) * 1986-04-25 1987-11-02 Hitachi Ltd 論理シミユレ−シヨン方法および装置
US5212650A (en) * 1986-09-12 1993-05-18 Digital Equipment Corporation Procedure and data structure for synthesis and transformation of logic circuit designs
EP0264334B1 (en) * 1986-10-16 1994-12-28 Fairchild Semiconductor Corporation Synchronous array logic circuit
US4829446A (en) * 1986-12-12 1989-05-09 Caeco, Inc. Method and apparatus for recording and rearranging representations of objects in a model of a group of objects located using a co-ordinate system
JP2535976B2 (ja) * 1987-11-17 1996-09-18 株式会社日立製作所 形態接続構成自動作成システム
US5067091A (en) * 1988-01-21 1991-11-19 Kabushiki Kaisha Toshiba Circuit design conversion apparatus
US5051938A (en) * 1989-06-23 1991-09-24 Hyduke Stanley M Simulation of selected logic circuit designs
US5243538B1 (en) * 1989-08-09 1995-11-07 Hitachi Ltd Comparison and verification system for logic circuits and method thereof
JP2531282B2 (ja) * 1989-12-22 1996-09-04 三菱電機株式会社 クロスト―ク検証装置
IL94115A (en) * 1990-04-18 1996-06-18 Ibm Israel Dynamic process for creating pseudo-random test templates for pompous hardware design violence
US5086477A (en) * 1990-08-07 1992-02-04 Northwest Technology Corp. Automated system for extracting design and layout information from an integrated circuit
JP2763985B2 (ja) * 1992-04-27 1998-06-11 三菱電機株式会社 論理シミュレーション装置
US5313398A (en) * 1992-07-23 1994-05-17 Carnegie Mellon University Method and apparatus for simulating a microelectronic circuit
US5481473A (en) * 1993-02-19 1996-01-02 International Business Machines Corporation System and method for building interconnections in a hierarchical circuit design
US5497334A (en) * 1993-02-19 1996-03-05 International Business Machines Corporation Application generator for use in verifying a hierarchical circuit design
US5435203A (en) 1993-09-16 1995-07-25 Teleflex Incorporated Manual shift twist adjustor
US5440720A (en) * 1993-09-20 1995-08-08 Cadence Design Systems, Inc. Architecture and method for data reduction in a system for analyzing geometric databases

Also Published As

Publication number Publication date
DE69521507D1 (de) 2001-08-02
WO1995030198A1 (en) 1995-11-09
US5559718A (en) 1996-09-24
DE69521507T2 (de) 2001-10-11
AU2369395A (en) 1995-11-29
EP0757819B1 (en) 2001-06-27
EP0757819A1 (en) 1997-02-12

Similar Documents

Publication Publication Date Title
ES2160162T3 (es) Sistema y procedimiento para la comprobacion a base de reglas de concepcion local.
Longacre An anatomy of speech notions
Bresnan et al. The thematic hierarchy and locative inversion in UG: A reply to Schachter’s comments
Waltz et al. Visual Analog Representations for Natural Languages Understanding.
NO913231D0 (no) Tankfylling i luften av ubemannet luftfartoey.
FI973088A0 (fi) Komposiittikalvosta muodostettava kosteuseste paristossa olevaa testilaitetta varten
IT9019264A1 (it) Metodo per associare testi in sistemi diagnostici automatici per produrre automaticamente azioni prescritte
BR9815245A (pt) Estrutura absorvente em camadas com uma regiãode camada heterogênea
DE69431311D1 (de) Vorrichtung zur Modellerzeugung durch Folienlaminierung
DE69125226D1 (de) Halbleiterspeicher mit getaktetem Zugriffskode für den Eintritt in den Prüfmodus
DE68914152D1 (de) Automatische Spiel- und Tonerzeugungseinheit in einer automatischen Musikanlage.
DE69416384D1 (de) Automatisches Testsystem mit integrierter Bussimulierung
DE69113087D1 (de) Vorrichtung zur Nachladung einer Batterie in einem Fahrzeug.
FI956243A0 (fi) Menetelmä dataan pääsyn toteuttamiseksi ensisijaiseen muistiin perustuvassa tietokannassa
JP2001155048A5 (ja) 設計支援システム及び設計支援方法
WANG Wind-driven circulation in the Potomac River[Final Report]
HUP0002732A2 (hu) Eljárás és rendszer automatikus jelölő készítéshez
FAGUNDO Hierarchical modeling for reliability analysis using Markov models(B. S./M. S. Thesis- MIT)
Holladay et al. Altered pronephric macrophage phagocytosis in tilapia(Oreochromis niloticus) exposed to 1 part-per-billion of the organophosphate insecticide, chlorpyrifos
BR9304839A (pt) Tanques de combustível aferidos à aceleração centrípeta em aeromodelos de vôo circular controlado
DE3762784D1 (de) Magnetischer blasenspeicher in hybrider technologie.
LIV et al. Earthquake risk and damage functions: An integrated preparedness and planning model applied to New Madrid[Final Report]
Borisenkov Simulating the carbon cycle in the atmosphere-ocean-biosphere system within the framework of linear and diffusion models.
DEUTSCH et al. Research, Development, Training, and Evaluation(RDTE) support delivery order 1: Computational cognitive models(Final Report, Mar. 1992- Apr. 1993)
INTRILAGATOR Integrated policy analysis of advanced technologies(economic planning and social factors)

Legal Events

Date Code Title Description
FG2A Definitive protection

Ref document number: 757819

Country of ref document: ES