ES2158841T3 - Gradacion expansiva de cpu con reconocimiento de subclase de interrupcion de e/s. - Google Patents

Gradacion expansiva de cpu con reconocimiento de subclase de interrupcion de e/s.

Info

Publication number
ES2158841T3
ES2158841T3 ES92113577T ES92113577T ES2158841T3 ES 2158841 T3 ES2158841 T3 ES 2158841T3 ES 92113577 T ES92113577 T ES 92113577T ES 92113577 T ES92113577 T ES 92113577T ES 2158841 T3 ES2158841 T3 ES 2158841T3
Authority
ES
Spain
Prior art keywords
guest
interruptions
cpu
controls
interruption
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES92113577T
Other languages
English (en)
Inventor
Norman Cho-Chun Chou
Peter Hermon Gum
Roger Eldred Hough
Moon Ju Kim
James Chester Mazurowski
Donald William Mccauley
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of ES2158841T3 publication Critical patent/ES2158841T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • G06F9/48Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806Task transfer initiation or dispatching
    • G06F9/4812Task transfer initiation or dispatching by interrupt, e.g. masked

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)
  • Bus Control (AREA)
  • Image Processing (AREA)

Abstract

UNA INTERFACE DE LA CPU QUE RECONOCE UN GRAN NUMERO DE COLAS DE INTERRUPCION DE E/S EN UN SISTEMA DE PROCESAMIENTO DE DATOS LOGICAMENTE DIVIDIDO. DIFERENTES PARTICIONES PUEDEN CONTENER DIFERENTES SISTEMAS OPERATIVOS HUESPED. LA INTERFACE DE LA CPU CONTROLA HASTA QUE PUNTO RESPONDEN LAS CPUS A LAS INTERRUPCIONES DE E/S PUESTAS EN NUMEROSAS COLAS CONTROLADAS POR EL HARDWARE. UN PROGRAMA HIPERVISOR PRINCIPAL COMUNICA CON LOS SISTEMAS OPERATIVOS HUESPED. LOS HUESPEDES UTILIZAN LAS INTERRUPCIONES DE E/S EN EL CONTROL DE LA COMUNICACION DE SUS PROGRAMAS EN LAS CPUS DE UN SISTEMA. LA INVENCION PERMITE QUE LAS DIFERENTES PARTICIONES HUESPED DEL SISTEMA EXCEDAN EL NUMERO DE SUBCLASES DE INTERRUPCION DE E/S (ISCS) CONSTRUIDAS EN EL SISTEMA, Y PERMITE QUE LOS CONTROLES DE COMUNICACION DE CADA SISTEMA OPERATIVO HUESPED SEA SENSIBLE A LAS DIFERENTES PRIORIDADES DE VARIOS PROGRAMAS QUE FUNCIONAN BAJO UN HUESPED RESPECTIVO. LA INVENCION PERMITE QUE LA CPU CONTROLE ESE SOPORTE ALERTANDO AL HUESPED DE LAS INTERRUPCIONES DE E/S PERMITIDAS, Y PROPORCIONA UN ACCESO CONTROLADO A LA CPU PARA PERMITIR EL MANEJO DEL HUESPED DIRECTO DE LAS INTERRUPCIONES DE E/S HUESPEDES.
ES92113577T 1991-08-29 1992-08-10 Gradacion expansiva de cpu con reconocimiento de subclase de interrupcion de e/s. Expired - Lifetime ES2158841T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/752,149 US5222215A (en) 1991-08-29 1991-08-29 Cpu expansive gradation of i/o interruption subclass recognition

Publications (1)

Publication Number Publication Date
ES2158841T3 true ES2158841T3 (es) 2001-09-16

Family

ID=25025099

Family Applications (1)

Application Number Title Priority Date Filing Date
ES92113577T Expired - Lifetime ES2158841T3 (es) 1991-08-29 1992-08-10 Gradacion expansiva de cpu con reconocimiento de subclase de interrupcion de e/s.

Country Status (7)

Country Link
US (1) US5222215A (es)
EP (1) EP0529384B1 (es)
JP (1) JP2525997B2 (es)
AT (1) ATE202857T1 (es)
CA (1) CA2068796A1 (es)
DE (1) DE69231909T2 (es)
ES (1) ES2158841T3 (es)

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DE69223303T2 (de) * 1991-09-27 1998-06-18 Sun Microsystems Inc Verfahren und Gerät für die dynamische Zuweisung von unadressierten Unterbrechungen
JPH06161779A (ja) * 1992-11-17 1994-06-10 Fujitsu Ltd データ処理装置の割込み制御方式
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CA2177850A1 (en) * 1993-12-01 1995-06-08 Thomas Dale Bissett Fault resilient/fault tolerant computing
US5555414A (en) * 1994-12-14 1996-09-10 International Business Machines Corporation Multiprocessing system including gating of host I/O and external enablement to guest enablement at polling intervals
JP2625402B2 (ja) * 1995-05-24 1997-07-02 日本電気株式会社 マイクロプロセッサ
US6643765B1 (en) * 1995-08-16 2003-11-04 Microunity Systems Engineering, Inc. Programmable processor with group floating point operations
GB2309103A (en) * 1996-01-09 1997-07-16 Nokia Mobile Phones Ltd Processing events
US5909582A (en) * 1996-04-26 1999-06-01 Nec Corporation Microcomputer having user mode interrupt function and supervisor mode interrupt function
WO1998009225A1 (en) * 1996-08-29 1998-03-05 Nematron Corporation Real time software system
US5790397A (en) 1996-09-17 1998-08-04 Marathon Technologies Corporation Fault resilient/fault tolerant computing
US6192418B1 (en) 1997-06-25 2001-02-20 Unisys Corp. System and method for performing external procedure calls from a client program to a server program while both are operating in a heterogenous computer
US6289391B1 (en) 1997-06-25 2001-09-11 Unisys Corp. System and method for performing external procedure calls from a server program to a client program while both are running in a heterogeneous computer
US6141697A (en) * 1997-06-25 2000-10-31 Unisys Corp. System and method for performing external procedure calls in heterogeneous computer systems utilizing program stacks
US6345329B1 (en) * 1999-02-19 2002-02-05 International Business Machines Corporation Method and apparatus for exchanging data using a queued direct input-output device
US6339802B1 (en) * 1999-02-19 2002-01-15 International Business Machines Corporation Computer program device and an apparatus for processing of data requests using a queued direct input-output device
US6339803B1 (en) * 1999-02-19 2002-01-15 International Business Machines Corporation Computer program product used for exchange and transfer of data having a queuing mechanism and utilizing a queued direct input-output device
US6957435B2 (en) * 2001-04-19 2005-10-18 International Business Machines Corporation Method and apparatus for allocating processor resources in a logically partitioned computer system
US7281075B2 (en) * 2003-04-24 2007-10-09 International Business Machines Corporation Virtualization of a global interrupt queue
US7130949B2 (en) * 2003-05-12 2006-10-31 International Business Machines Corporation Managing input/output interruptions in non-dedicated interruption hardware environments
US7877747B2 (en) 2004-02-20 2011-01-25 Hewlett-Packard Development Company, L.P. Flexible operating system operable as either native or as virtualized
US8214622B2 (en) 2004-05-27 2012-07-03 International Business Machines Corporation Facilitating management of storage of a pageable mode virtual environment absent intervention of a host of the environment
US7941799B2 (en) 2004-05-27 2011-05-10 International Business Machines Corporation Interpreting I/O operation requests from pageable guests without host intervention
US7478185B2 (en) * 2007-01-05 2009-01-13 International Business Machines Corporation Directly initiating by external adapters the setting of interruption initiatives
US7698531B2 (en) * 2007-03-28 2010-04-13 International Business Machines Corporation Workload management in virtualized data processing environment
US8219995B2 (en) * 2007-03-28 2012-07-10 International Business Machins Corporation Capturing hardware statistics for partitions to enable dispatching and scheduling efficiency
US7617375B2 (en) * 2007-03-28 2009-11-10 International Business Machines Corporation Workload management in virtualized data processing environment
US7698530B2 (en) * 2007-03-28 2010-04-13 International Business Machines Corporation Workload management in virtualized data processing environment
GB2454817B (en) * 2008-01-10 2012-07-04 Ibm Method and device for interrupt handling in a logically partitioned data processing system
US8527715B2 (en) 2008-02-26 2013-09-03 International Business Machines Corporation Providing a shared memory translation facility
US8458438B2 (en) * 2008-02-26 2013-06-04 International Business Machines Corporation System, method and computer program product for providing quiesce filtering for shared memory
US8380907B2 (en) * 2008-02-26 2013-02-19 International Business Machines Corporation Method, system and computer program product for providing filtering of GUEST2 quiesce requests
US8140834B2 (en) * 2008-02-26 2012-03-20 International Business Machines Corporation System, method and computer program product for providing a programmable quiesce filtering register
US8234432B2 (en) * 2009-01-26 2012-07-31 Advanced Micro Devices, Inc. Memory structure to store interrupt state for inactive guests
US8489789B2 (en) * 2010-02-05 2013-07-16 Advanced Micro Devices, Inc. Interrupt virtualization
US8478922B2 (en) * 2010-06-23 2013-07-02 International Business Machines Corporation Controlling a rate at which adapter interruption requests are processed
US8762615B2 (en) 2011-12-21 2014-06-24 International Business Machines Corporation Dequeue operation using mask vector to manage input/output interruptions
US8819648B2 (en) * 2012-07-20 2014-08-26 International Business Machines Corporation Control flow management for execution of dynamically translated non-native code in a virtual hosting environment
US9009368B2 (en) 2012-10-23 2015-04-14 Advanced Micro Devices, Inc. Interrupt latency performance counters
US9760511B2 (en) * 2014-10-08 2017-09-12 International Business Machines Corporation Efficient interruption routing for a multithreaded processor
US10282327B2 (en) * 2017-01-19 2019-05-07 International Business Machines Corporation Test pending external interruption instruction
US11989144B2 (en) 2021-07-30 2024-05-21 Advanced Micro Devices, Inc. Centralized interrupt handling for chiplet processing units

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US4564903A (en) * 1983-10-05 1986-01-14 International Business Machines Corporation Partitioned multiprocessor programming system
JPS6258341A (ja) * 1985-09-03 1987-03-14 Fujitsu Ltd 入出力割込処理方式
US4843541A (en) * 1987-07-29 1989-06-27 International Business Machines Corporation Logical resource partitioning of a data processing system
EP0419723B1 (de) * 1989-09-29 1995-01-11 Siemens Nixdorf Informationssysteme Aktiengesellschaft Verfahren und Unterbrechungssteuerung zur Behandlung von Unterbrechungsanforderungen bei Ein-/Ausgabeoperationen in einem virtuellen Maschinensystem

Also Published As

Publication number Publication date
EP0529384A1 (en) 1993-03-03
CA2068796A1 (en) 1993-03-01
ATE202857T1 (de) 2001-07-15
JP2525997B2 (ja) 1996-08-21
DE69231909T2 (de) 2001-11-29
DE69231909D1 (de) 2001-08-09
US5222215A (en) 1993-06-22
EP0529384B1 (en) 2001-07-04
JPH05204679A (ja) 1993-08-13

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