ES2119143T3 - Disposicion para la transmision de datos a traves de un bus. - Google Patents
Disposicion para la transmision de datos a traves de un bus.Info
- Publication number
- ES2119143T3 ES2119143T3 ES94900046T ES94900046T ES2119143T3 ES 2119143 T3 ES2119143 T3 ES 2119143T3 ES 94900046 T ES94900046 T ES 94900046T ES 94900046 T ES94900046 T ES 94900046T ES 2119143 T3 ES2119143 T3 ES 2119143T3
- Authority
- ES
- Spain
- Prior art keywords
- data
- pct
- bus
- transmission
- transmitting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4009—Coupling between buses with data restructuring
- G06F13/4018—Coupling between buses with data restructuring with data-width conversion
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Bus Control (AREA)
- Vehicle Body Suspensions (AREA)
- Measuring Pulse, Heart Rate, Blood Pressure Or Blood Flow (AREA)
- Small-Scale Networks (AREA)
Abstract
LA INVENCION SE REFIERE A UNA DISPOSICION PARA TRANSMISION DE DATOS A PARTIR DE UN BUS (2,6,7), QUE DISPONE DE UNA UNIDAD (1,4,5) CENTRAL QUE INICIA LA TRANSMISION DE DATOS Y UNA O VARIAS UNIDADES (3,8,9) PERIFERICAS LIGADAS UNA A OTRA POR MEDIO DEL BUS. EN AL MENOS UNO DE LOS COMPONENTES, JUNTO A LAS PRIMERAS LINEAS DE CONTROL Y A LAS LINEAS DE DATOS PARA LA TRANSMISION DE UNA PALABRA DE DATOS CON UNA PRIMERA AMPLITUD DE DATOS, SE DISPONE ADEMAS DE LINEAS DE CONTROL Y LINEAS DE DATOS PARA LA TRANSMISION DE UNA PALABRA DE DATOS TENIENDO UNA SEGUNDA AMPLITUD DE DATOS. ESTO ESTA DISEÑADO DE TAL MODO QUE LOS COMPONENTES CON DATOS DIFERENTES DE AMPLITUDES DE BUS PUEDEN COMUNICARSE UNO CON OTRO MEDIANTE TRANSMISION DE PALABRAS DE DATOS TENIENDO LA AMPLITUD DE DATOS EXISTENTE MAS PEQUEÑA. EN EQUIPOS DE AUTOMACION, LA INVENCION PERMITE CUALQUIER COMBINACION DE COMPONENTES DE DIFERENTES CLASES DE CAPACIDAD. LA INVENCION SE UTILIZA EN SISTEMAS BUS.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE4239461A DE4239461A1 (de) | 1992-11-24 | 1992-11-24 | Anordnung zur Übertragung von Daten über einen Bus |
Publications (1)
Publication Number | Publication Date |
---|---|
ES2119143T3 true ES2119143T3 (es) | 1998-10-01 |
Family
ID=6473516
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ES94900046T Expired - Lifetime ES2119143T3 (es) | 1992-11-24 | 1993-11-18 | Disposicion para la transmision de datos a traves de un bus. |
Country Status (7)
Country | Link |
---|---|
US (1) | US5608882A (es) |
EP (1) | EP0671033B1 (es) |
JP (1) | JP2615383B2 (es) |
AT (1) | ATE168797T1 (es) |
DE (2) | DE4239461A1 (es) |
ES (1) | ES2119143T3 (es) |
WO (1) | WO1994012936A1 (es) |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3566364B2 (ja) * | 1994-12-22 | 2004-09-15 | キヤノン株式会社 | データ処理装置及び方法 |
US5764927A (en) * | 1995-09-29 | 1998-06-09 | Allen Bradley Company, Inc. | Backplane data transfer technique for industrial automation controllers |
DE19636381C1 (de) * | 1996-09-09 | 1998-03-12 | Ibm | Bus mit anforderungsabhängiger Anpassung der in beiden Richtungen zur Verfügung stehenden Bandbreite |
US6351786B2 (en) | 1998-08-24 | 2002-02-26 | Racal Instr Inc | VXI backplane system improvements and methods |
CA2265346A1 (en) * | 1999-03-17 | 2000-09-17 | Pmc-Sierra Ltd. | Pos-phy interface for interconnection of physical layer devices and link layer devices |
TW507128B (en) * | 2001-07-12 | 2002-10-21 | Via Tech Inc | Data memory controller supporting the data bus invert |
FR2829337B1 (fr) * | 2001-09-03 | 2003-10-31 | Schneider Automation | Equipement d'automatisme connecte a un reseau tcp/ip |
JP2004171445A (ja) * | 2002-11-22 | 2004-06-17 | Renesas Technology Corp | 半導体データ処理装置及びデータ処理システム |
DE10346570A1 (de) * | 2003-10-07 | 2005-05-19 | Siemens Ag | Bussystem und Buscontroller für elektronische Systeme |
US8239594B2 (en) * | 2005-11-10 | 2012-08-07 | Datacard Corporation | Modular card issuance system and method of operation |
CN102759952B (zh) * | 2011-04-29 | 2017-04-12 | 富泰华工业(深圳)有限公司 | 嵌入式系统 |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3133407C2 (de) * | 1981-08-24 | 1984-07-26 | Siemens AG, 1000 Berlin und 8000 München | Programmgesteuerter Rechner |
US4716527A (en) * | 1984-12-10 | 1987-12-29 | Ing. C. Olivetti | Bus converter |
JPS61175845A (ja) * | 1985-01-31 | 1986-08-07 | Toshiba Corp | マイクロプロセツサシステム |
JPS6226561A (ja) * | 1985-07-26 | 1987-02-04 | Toshiba Corp | パ−ソナルコンピユ−タ |
US5045998A (en) * | 1988-05-26 | 1991-09-03 | International Business Machines Corporation | Method and apparatus for selectively posting write cycles using the 82385 cache controller |
US5038317A (en) * | 1988-07-25 | 1991-08-06 | Allen-Bradley Company, Inc. | Programmable controller module rack with a relative rack slot addressing mechanism |
DE69034165T2 (de) * | 1990-07-20 | 2005-09-22 | Infineon Technologies Ag | Mikroprozessor mit einer Vielzahl von Buskonfigurationen |
DE69228975T2 (de) * | 1991-10-28 | 1999-11-18 | Eastman Kodak Co., Rochester | Steuerungsschaltung zur Datenübertragung von einem VME-Bus zu einer SCSI-Platteneinheit |
US5335340A (en) * | 1992-05-29 | 1994-08-02 | The Whitaker Corporation | Byte-swap hardware simulator for a sixteen bit microprocessor coupled to an eight bit peripheral unit |
US5423009A (en) * | 1993-02-18 | 1995-06-06 | Sierra Semiconductor Corporation | Dynamic sizing bus controller that allows unrestricted byte enable patterns |
-
1992
- 1992-11-24 DE DE4239461A patent/DE4239461A1/de not_active Withdrawn
-
1993
- 1993-11-18 DE DE59308811T patent/DE59308811D1/de not_active Expired - Lifetime
- 1993-11-18 JP JP6512633A patent/JP2615383B2/ja not_active Expired - Fee Related
- 1993-11-18 EP EP94900046A patent/EP0671033B1/de not_active Expired - Lifetime
- 1993-11-18 AT AT94900046T patent/ATE168797T1/de not_active IP Right Cessation
- 1993-11-18 WO PCT/DE1993/001098 patent/WO1994012936A1/de active IP Right Grant
- 1993-11-18 ES ES94900046T patent/ES2119143T3/es not_active Expired - Lifetime
- 1993-11-18 US US08/436,403 patent/US5608882A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JPH07509090A (ja) | 1995-10-05 |
DE4239461A1 (de) | 1994-05-26 |
EP0671033B1 (de) | 1998-07-22 |
WO1994012936A1 (de) | 1994-06-09 |
DE59308811D1 (de) | 1998-08-27 |
US5608882A (en) | 1997-03-04 |
JP2615383B2 (ja) | 1997-05-28 |
ATE168797T1 (de) | 1998-08-15 |
EP0671033A1 (de) | 1995-09-13 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
FG2A | Definitive protection |
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