ES2117564A1 - Transistor inecuacional o pseudoneuronal. - Google Patents
Transistor inecuacional o pseudoneuronal.Info
- Publication number
- ES2117564A1 ES2117564A1 ES09600923A ES9600923A ES2117564A1 ES 2117564 A1 ES2117564 A1 ES 2117564A1 ES 09600923 A ES09600923 A ES 09600923A ES 9600923 A ES9600923 A ES 9600923A ES 2117564 A1 ES2117564 A1 ES 2117564A1
- Authority
- ES
- Spain
- Prior art keywords
- transistor
- inputs
- data
- pseudoneuronal
- inequational
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Logic Circuits (AREA)
Abstract
TRANSISTOR INECUACIONAL O PSEUDONEURONAL, CONSTITUIDO POR UN CUERPO DE PLANTA Y ESTRUCTURA ALARGADA, SOBRE EL CUAL SE MONTA UN CHIP (1), DE FINOS HILOS (2) CONECTADOS ENTRE SI FORMANDO UN PAQUETE (3), LOS CUALES FORMAN UNA BASE DE CONEXIONES (4) PROLONGADAS HASTA LAS PATILLAS (5). LOS ELEMENTOS INTERNOS SON EL CHIP DE MEMORIA (6) Y EL CHIP DE ENTRADA Y SALIDA DE DATOS (7). LOS ELEMENTOS EXTERNOS SON LA FUENTE DE ALIMENTACION (8), UNA PUERTA LOGICA (9) Y UN DRENADOR REGULADOR (10), ENCARGADOS DE LAS ENTRADAS Y SALIDAS DEL PROCESO. EL PROCESO ES REALIZADO POR LA COMBINACION DE LOS FLUJOS O ENTRADAS DE DATOS (14), (15) Y (16), DE LOS CUALES FLUYEN PORTADORES DE CORRIENTE HACIA EL EMISOR (11), DESDE DONDE SON PROYECTADOS LOS DATOS HASTA EL COLECTOR (13), AUNQUE SIEMPRE ENTRE AMBOS COMO EJE SEMICONDUCTOR LA BASE EMISOR (12) REGULADORA DEL PROCESO. SIMULANDO UNA O MAS PUERTAS LOGICAS CON UN UNICO TRANSISTOR, POR LAS ENTRADAS DE DOS O MAS DATOS EN UN UNICO TRANSISTOR.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
ES9600923A ES2117564B1 (es) | 1996-04-24 | 1996-04-24 | Transistor inecuacional o pseudoneuronal. |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
ES9600923A ES2117564B1 (es) | 1996-04-24 | 1996-04-24 | Transistor inecuacional o pseudoneuronal. |
Publications (2)
Publication Number | Publication Date |
---|---|
ES2117564A1 true ES2117564A1 (es) | 1998-08-01 |
ES2117564B1 ES2117564B1 (es) | 1999-04-01 |
Family
ID=8294591
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ES9600923A Expired - Lifetime ES2117564B1 (es) | 1996-04-24 | 1996-04-24 | Transistor inecuacional o pseudoneuronal. |
Country Status (1)
Country | Link |
---|---|
ES (1) | ES2117564B1 (es) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0578821A1 (en) * | 1991-03-21 | 1994-01-19 | SHIBATA, Tadashi | Semiconductor device |
EP0685806A1 (en) * | 1993-02-22 | 1995-12-06 | SHIBATA, Tadashi | Semiconductor device |
-
1996
- 1996-04-24 ES ES9600923A patent/ES2117564B1/es not_active Expired - Lifetime
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0578821A1 (en) * | 1991-03-21 | 1994-01-19 | SHIBATA, Tadashi | Semiconductor device |
EP0685806A1 (en) * | 1993-02-22 | 1995-12-06 | SHIBATA, Tadashi | Semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
ES2117564B1 (es) | 1999-04-01 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
EC2A | Search report published |
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